1 /*
2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/mlx5/driver.h>
35 #include "mlx5_core.h"
36
mlx5_qos_tsar_type_supported(struct mlx5_core_dev * dev,int type,u8 hierarchy)37 bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy)
38 {
39 int cap;
40
41 switch (hierarchy) {
42 case SCHEDULING_HIERARCHY_E_SWITCH:
43 cap = MLX5_CAP_QOS(dev, esw_tsar_type);
44 break;
45 case SCHEDULING_HIERARCHY_NIC:
46 cap = MLX5_CAP_QOS(dev, nic_tsar_type);
47 break;
48 default:
49 return false;
50 }
51
52 switch (type) {
53 case TSAR_ELEMENT_TSAR_TYPE_DWRR:
54 return cap & TSAR_TYPE_CAP_MASK_DWRR;
55 case TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN:
56 return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN;
57 case TSAR_ELEMENT_TSAR_TYPE_ETS:
58 return cap & TSAR_TYPE_CAP_MASK_ETS;
59 case TSAR_ELEMENT_TSAR_TYPE_TC_ARB:
60 return cap & TSAR_TYPE_CAP_MASK_TC_ARB;
61 }
62
63 return false;
64 }
65
mlx5_qos_element_type_supported(struct mlx5_core_dev * dev,int type,u8 hierarchy)66 bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hierarchy)
67 {
68 int cap;
69
70 switch (hierarchy) {
71 case SCHEDULING_HIERARCHY_E_SWITCH:
72 cap = MLX5_CAP_QOS(dev, esw_element_type);
73 break;
74 case SCHEDULING_HIERARCHY_NIC:
75 cap = MLX5_CAP_QOS(dev, nic_element_type);
76 break;
77 default:
78 return false;
79 }
80
81 switch (type) {
82 case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR:
83 return cap & ELEMENT_TYPE_CAP_MASK_TSAR;
84 case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT:
85 return cap & ELEMENT_TYPE_CAP_MASK_VPORT;
86 case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC:
87 return cap & ELEMENT_TYPE_CAP_MASK_VPORT_TC;
88 case SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC:
89 return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC;
90 case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP:
91 return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP;
92 case SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT:
93 return cap & ELEMENT_TYPE_CAP_MASK_RATE_LIMIT;
94 }
95
96 return false;
97 }
98
99 /* Scheduling element fw management */
mlx5_create_scheduling_element_cmd(struct mlx5_core_dev * dev,u8 hierarchy,void * ctx,u32 * element_id)100 int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
101 void *ctx, u32 *element_id)
102 {
103 u32 out[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {};
104 u32 in[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {};
105 void *schedc;
106 int err;
107
108 schedc = MLX5_ADDR_OF(create_scheduling_element_in, in,
109 scheduling_context);
110 MLX5_SET(create_scheduling_element_in, in, opcode,
111 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT);
112 MLX5_SET(create_scheduling_element_in, in, scheduling_hierarchy,
113 hierarchy);
114 memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));
115
116 err = mlx5_cmd_exec_inout(dev, create_scheduling_element, in, out);
117 if (err)
118 return err;
119
120 *element_id = MLX5_GET(create_scheduling_element_out, out,
121 scheduling_element_id);
122 return 0;
123 }
124
mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev * dev,u8 hierarchy,void * ctx,u32 element_id,u32 modify_bitmask)125 int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
126 void *ctx, u32 element_id,
127 u32 modify_bitmask)
128 {
129 u32 in[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {};
130 void *schedc;
131
132 schedc = MLX5_ADDR_OF(modify_scheduling_element_in, in,
133 scheduling_context);
134 MLX5_SET(modify_scheduling_element_in, in, opcode,
135 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT);
136 MLX5_SET(modify_scheduling_element_in, in, scheduling_element_id,
137 element_id);
138 MLX5_SET(modify_scheduling_element_in, in, modify_bitmask,
139 modify_bitmask);
140 MLX5_SET(modify_scheduling_element_in, in, scheduling_hierarchy,
141 hierarchy);
142 memcpy(schedc, ctx, MLX5_ST_SZ_BYTES(scheduling_context));
143
144 return mlx5_cmd_exec_in(dev, modify_scheduling_element, in);
145 }
146
mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev * dev,u8 hierarchy,u32 element_id)147 int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
148 u32 element_id)
149 {
150 u32 in[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {};
151
152 MLX5_SET(destroy_scheduling_element_in, in, opcode,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT);
154 MLX5_SET(destroy_scheduling_element_in, in, scheduling_element_id,
155 element_id);
156 MLX5_SET(destroy_scheduling_element_in, in, scheduling_hierarchy,
157 hierarchy);
158
159 return mlx5_cmd_exec_in(dev, destroy_scheduling_element, in);
160 }
161
mlx5_rl_are_equal_raw(struct mlx5_rl_entry * entry,void * rl_in,u16 uid)162 static bool mlx5_rl_are_equal_raw(struct mlx5_rl_entry *entry, void *rl_in,
163 u16 uid)
164 {
165 return (!memcmp(entry->rl_raw, rl_in, sizeof(entry->rl_raw)) &&
166 entry->uid == uid);
167 }
168
169 /* Finds an entry where we can register the given rate
170 * If the rate already exists, return the entry where it is registered,
171 * otherwise return the first available entry.
172 * If the table is full, return NULL
173 */
find_rl_entry(struct mlx5_rl_table * table,void * rl_in,u16 uid,bool dedicated)174 static struct mlx5_rl_entry *find_rl_entry(struct mlx5_rl_table *table,
175 void *rl_in, u16 uid, bool dedicated)
176 {
177 struct mlx5_rl_entry *ret_entry = NULL;
178 bool empty_found = false;
179 int i;
180
181 lockdep_assert_held(&table->rl_lock);
182 WARN_ON(!table->rl_entry);
183
184 for (i = 0; i < table->max_size; i++) {
185 if (dedicated) {
186 if (!table->rl_entry[i].refcount)
187 return &table->rl_entry[i];
188 continue;
189 }
190
191 if (table->rl_entry[i].refcount) {
192 if (table->rl_entry[i].dedicated)
193 continue;
194 if (mlx5_rl_are_equal_raw(&table->rl_entry[i], rl_in,
195 uid))
196 return &table->rl_entry[i];
197 } else if (!empty_found) {
198 empty_found = true;
199 ret_entry = &table->rl_entry[i];
200 }
201 }
202
203 return ret_entry;
204 }
205
mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev * dev,struct mlx5_rl_entry * entry,bool set)206 static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev,
207 struct mlx5_rl_entry *entry, bool set)
208 {
209 u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {};
210 void *pp_context;
211
212 pp_context = MLX5_ADDR_OF(set_pp_rate_limit_in, in, ctx);
213 MLX5_SET(set_pp_rate_limit_in, in, opcode,
214 MLX5_CMD_OP_SET_PP_RATE_LIMIT);
215 MLX5_SET(set_pp_rate_limit_in, in, uid, entry->uid);
216 MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, entry->index);
217 if (set)
218 memcpy(pp_context, entry->rl_raw, sizeof(entry->rl_raw));
219 return mlx5_cmd_exec_in(dev, set_pp_rate_limit, in);
220 }
221
mlx5_rl_is_in_range(struct mlx5_core_dev * dev,u32 rate)222 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate)
223 {
224 struct mlx5_rl_table *table = &dev->priv.rl_table;
225
226 return (rate <= table->max_rate && rate >= table->min_rate);
227 }
228 EXPORT_SYMBOL(mlx5_rl_is_in_range);
229
mlx5_rl_are_equal(struct mlx5_rate_limit * rl_0,struct mlx5_rate_limit * rl_1)230 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
231 struct mlx5_rate_limit *rl_1)
232 {
233 return ((rl_0->rate == rl_1->rate) &&
234 (rl_0->max_burst_sz == rl_1->max_burst_sz) &&
235 (rl_0->typical_pkt_sz == rl_1->typical_pkt_sz));
236 }
237 EXPORT_SYMBOL(mlx5_rl_are_equal);
238
mlx5_rl_table_get(struct mlx5_rl_table * table)239 static int mlx5_rl_table_get(struct mlx5_rl_table *table)
240 {
241 int i;
242
243 lockdep_assert_held(&table->rl_lock);
244
245 if (table->rl_entry) {
246 table->refcount++;
247 return 0;
248 }
249
250 table->rl_entry = kzalloc_objs(struct mlx5_rl_entry, table->max_size);
251 if (!table->rl_entry)
252 return -ENOMEM;
253
254 /* The index represents the index in HW rate limit table
255 * Index 0 is reserved for unlimited rate
256 */
257 for (i = 0; i < table->max_size; i++)
258 table->rl_entry[i].index = i + 1;
259
260 table->refcount++;
261 return 0;
262 }
263
mlx5_rl_table_put(struct mlx5_rl_table * table)264 static void mlx5_rl_table_put(struct mlx5_rl_table *table)
265 {
266 lockdep_assert_held(&table->rl_lock);
267 if (--table->refcount)
268 return;
269
270 kfree(table->rl_entry);
271 table->rl_entry = NULL;
272 }
273
mlx5_rl_table_free(struct mlx5_core_dev * dev,struct mlx5_rl_table * table)274 static void mlx5_rl_table_free(struct mlx5_core_dev *dev, struct mlx5_rl_table *table)
275 {
276 int i;
277
278 if (!table->rl_entry)
279 return;
280
281 /* Clear all configured rates */
282 for (i = 0; i < table->max_size; i++)
283 if (table->rl_entry[i].refcount)
284 mlx5_set_pp_rate_limit_cmd(dev, &table->rl_entry[i], false);
285 kfree(table->rl_entry);
286 }
287
mlx5_rl_entry_get(struct mlx5_rl_entry * entry)288 static void mlx5_rl_entry_get(struct mlx5_rl_entry *entry)
289 {
290 entry->refcount++;
291 }
292
293 static void
mlx5_rl_entry_put(struct mlx5_core_dev * dev,struct mlx5_rl_entry * entry)294 mlx5_rl_entry_put(struct mlx5_core_dev *dev, struct mlx5_rl_entry *entry)
295 {
296 entry->refcount--;
297 if (!entry->refcount)
298 mlx5_set_pp_rate_limit_cmd(dev, entry, false);
299 }
300
mlx5_rl_add_rate_raw(struct mlx5_core_dev * dev,void * rl_in,u16 uid,bool dedicated_entry,u16 * index)301 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
302 bool dedicated_entry, u16 *index)
303 {
304 struct mlx5_rl_table *table = &dev->priv.rl_table;
305 struct mlx5_rl_entry *entry;
306 u32 rate;
307 int err;
308
309 if (!table->max_size)
310 return -EOPNOTSUPP;
311
312 rate = MLX5_GET(set_pp_rate_limit_context, rl_in, rate_limit);
313 if (!rate || !mlx5_rl_is_in_range(dev, rate)) {
314 mlx5_core_err(dev, "Invalid rate: %u, should be %u to %u\n",
315 rate, table->min_rate, table->max_rate);
316 return -EINVAL;
317 }
318
319 mutex_lock(&table->rl_lock);
320 err = mlx5_rl_table_get(table);
321 if (err)
322 goto out;
323
324 entry = find_rl_entry(table, rl_in, uid, dedicated_entry);
325 if (!entry) {
326 mlx5_core_err(dev, "Max number of %u rates reached\n",
327 table->max_size);
328 err = -ENOSPC;
329 goto rl_err;
330 }
331 if (!entry->refcount) {
332 /* new rate limit */
333 memcpy(entry->rl_raw, rl_in, sizeof(entry->rl_raw));
334 entry->uid = uid;
335 err = mlx5_set_pp_rate_limit_cmd(dev, entry, true);
336 if (err) {
337 mlx5_core_err(
338 dev,
339 "Failed configuring rate limit(err %d): rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
340 err, rate,
341 MLX5_GET(set_pp_rate_limit_context, rl_in,
342 burst_upper_bound),
343 MLX5_GET(set_pp_rate_limit_context, rl_in,
344 typical_packet_size));
345 goto rl_err;
346 }
347
348 entry->dedicated = dedicated_entry;
349 }
350 mlx5_rl_entry_get(entry);
351 *index = entry->index;
352 mutex_unlock(&table->rl_lock);
353 return 0;
354
355 rl_err:
356 mlx5_rl_table_put(table);
357 out:
358 mutex_unlock(&table->rl_lock);
359 return err;
360 }
361 EXPORT_SYMBOL(mlx5_rl_add_rate_raw);
362
mlx5_rl_remove_rate_raw(struct mlx5_core_dev * dev,u16 index)363 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index)
364 {
365 struct mlx5_rl_table *table = &dev->priv.rl_table;
366 struct mlx5_rl_entry *entry;
367
368 mutex_lock(&table->rl_lock);
369 entry = &table->rl_entry[index - 1];
370 mlx5_rl_entry_put(dev, entry);
371 mlx5_rl_table_put(table);
372 mutex_unlock(&table->rl_lock);
373 }
374 EXPORT_SYMBOL(mlx5_rl_remove_rate_raw);
375
mlx5_rl_add_rate(struct mlx5_core_dev * dev,u16 * index,struct mlx5_rate_limit * rl)376 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
377 struct mlx5_rate_limit *rl)
378 {
379 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
380
381 MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
382 MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
383 rl->max_burst_sz);
384 MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
385 rl->typical_pkt_sz);
386
387 return mlx5_rl_add_rate_raw(dev, rl_raw,
388 MLX5_CAP_QOS(dev, packet_pacing_uid) ?
389 MLX5_SHARED_RESOURCE_UID : 0,
390 false, index);
391 }
392 EXPORT_SYMBOL(mlx5_rl_add_rate);
393
mlx5_rl_remove_rate(struct mlx5_core_dev * dev,struct mlx5_rate_limit * rl)394 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl)
395 {
396 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)] = {};
397 struct mlx5_rl_table *table = &dev->priv.rl_table;
398 struct mlx5_rl_entry *entry = NULL;
399
400 /* 0 is a reserved value for unlimited rate */
401 if (rl->rate == 0)
402 return;
403
404 MLX5_SET(set_pp_rate_limit_context, rl_raw, rate_limit, rl->rate);
405 MLX5_SET(set_pp_rate_limit_context, rl_raw, burst_upper_bound,
406 rl->max_burst_sz);
407 MLX5_SET(set_pp_rate_limit_context, rl_raw, typical_packet_size,
408 rl->typical_pkt_sz);
409
410 mutex_lock(&table->rl_lock);
411 entry = find_rl_entry(table, rl_raw,
412 MLX5_CAP_QOS(dev, packet_pacing_uid) ?
413 MLX5_SHARED_RESOURCE_UID : 0, false);
414 if (!entry || !entry->refcount) {
415 mlx5_core_warn(dev, "Rate %u, max_burst_sz %u typical_pkt_sz %u are not configured\n",
416 rl->rate, rl->max_burst_sz, rl->typical_pkt_sz);
417 goto out;
418 }
419 mlx5_rl_entry_put(dev, entry);
420 mlx5_rl_table_put(table);
421 out:
422 mutex_unlock(&table->rl_lock);
423 }
424 EXPORT_SYMBOL(mlx5_rl_remove_rate);
425
mlx5_init_rl_table(struct mlx5_core_dev * dev)426 int mlx5_init_rl_table(struct mlx5_core_dev *dev)
427 {
428 struct mlx5_rl_table *table = &dev->priv.rl_table;
429
430 if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing)) {
431 table->max_size = 0;
432 return 0;
433 }
434
435 mutex_init(&table->rl_lock);
436
437 /* First entry is reserved for unlimited rate */
438 table->max_size = MLX5_CAP_QOS(dev, packet_pacing_rate_table_size) - 1;
439 table->max_rate = MLX5_CAP_QOS(dev, packet_pacing_max_rate);
440 table->min_rate = MLX5_CAP_QOS(dev, packet_pacing_min_rate);
441
442 mlx5_core_info(dev, "Rate limit: %u rates are supported, range: %uMbps to %uMbps\n",
443 table->max_size,
444 table->min_rate >> 10,
445 table->max_rate >> 10);
446
447 return 0;
448 }
449
mlx5_cleanup_rl_table(struct mlx5_core_dev * dev)450 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev)
451 {
452 struct mlx5_rl_table *table = &dev->priv.rl_table;
453
454 if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, packet_pacing))
455 return;
456
457 mlx5_rl_table_free(dev, table);
458 mutex_destroy(&table->rl_lock);
459 }
460