1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 gpio2 = &gpio2; 26 gpio3 = &gpio3; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 serial2 = &uart2; 30 i2c0 = &i2c0; 31 i2c1 = &i2c1; 32 i2c2 = &i2c2; 33 i2c3 = &i2c3; 34 }; 35 36 cpus { 37 #address-cells = <2>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0x0 0x0>; 44 clocks = <&cru ARMCLK>; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&CPU_SLEEP>; 47 dynamic-power-coefficient = <120>; 48 enable-method = "psci"; 49 operating-points-v2 = <&cpu0_opp_table>; 50 i-cache-size = <0x8000>; 51 i-cache-line-size = <64>; 52 i-cache-sets = <256>; 53 d-cache-size = <0x8000>; 54 d-cache-line-size = <64>; 55 d-cache-sets = <128>; 56 next-level-cache = <&l2_cache>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0 0x1>; 63 clocks = <&cru ARMCLK>; 64 #cooling-cells = <2>; 65 cpu-idle-states = <&CPU_SLEEP>; 66 dynamic-power-coefficient = <120>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 i-cache-size = <0x8000>; 70 i-cache-line-size = <64>; 71 i-cache-sets = <256>; 72 d-cache-size = <0x8000>; 73 d-cache-line-size = <64>; 74 d-cache-sets = <128>; 75 next-level-cache = <&l2_cache>; 76 }; 77 78 cpu2: cpu@2 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x2>; 82 clocks = <&cru ARMCLK>; 83 #cooling-cells = <2>; 84 cpu-idle-states = <&CPU_SLEEP>; 85 dynamic-power-coefficient = <120>; 86 enable-method = "psci"; 87 operating-points-v2 = <&cpu0_opp_table>; 88 i-cache-size = <0x8000>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <256>; 91 d-cache-size = <0x8000>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_cache>; 95 }; 96 97 cpu3: cpu@3 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0 0x3>; 101 clocks = <&cru ARMCLK>; 102 #cooling-cells = <2>; 103 cpu-idle-states = <&CPU_SLEEP>; 104 dynamic-power-coefficient = <120>; 105 enable-method = "psci"; 106 operating-points-v2 = <&cpu0_opp_table>; 107 i-cache-size = <0x8000>; 108 i-cache-line-size = <64>; 109 i-cache-sets = <256>; 110 d-cache-size = <0x8000>; 111 d-cache-line-size = <64>; 112 d-cache-sets = <128>; 113 next-level-cache = <&l2_cache>; 114 }; 115 116 idle-states { 117 entry-method = "psci"; 118 119 CPU_SLEEP: cpu-sleep { 120 compatible = "arm,idle-state"; 121 local-timer-stop; 122 arm,psci-suspend-param = <0x0010000>; 123 entry-latency-us = <120>; 124 exit-latency-us = <250>; 125 min-residency-us = <900>; 126 }; 127 }; 128 129 l2_cache: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 cache-size = <0x40000>; 134 cache-line-size = <64>; 135 cache-sets = <256>; 136 }; 137 }; 138 139 cpu0_opp_table: opp-table-0 { 140 compatible = "operating-points-v2"; 141 opp-shared; 142 143 opp-408000000 { 144 opp-hz = /bits/ 64 <408000000>; 145 opp-microvolt = <950000>; 146 clock-latency-ns = <40000>; 147 opp-suspend; 148 }; 149 opp-600000000 { 150 opp-hz = /bits/ 64 <600000000>; 151 opp-microvolt = <950000>; 152 clock-latency-ns = <40000>; 153 }; 154 opp-816000000 { 155 opp-hz = /bits/ 64 <816000000>; 156 opp-microvolt = <1000000>; 157 clock-latency-ns = <40000>; 158 }; 159 opp-1008000000 { 160 opp-hz = /bits/ 64 <1008000000>; 161 opp-microvolt = <1100000>; 162 clock-latency-ns = <40000>; 163 }; 164 opp-1200000000 { 165 opp-hz = /bits/ 64 <1200000000>; 166 opp-microvolt = <1225000>; 167 clock-latency-ns = <40000>; 168 }; 169 opp-1296000000 { 170 opp-hz = /bits/ 64 <1296000000>; 171 opp-microvolt = <1300000>; 172 clock-latency-ns = <40000>; 173 }; 174 }; 175 176 analog_sound: analog-sound { 177 compatible = "simple-audio-card"; 178 simple-audio-card,format = "i2s"; 179 simple-audio-card,mclk-fs = <256>; 180 simple-audio-card,name = "Analog"; 181 status = "disabled"; 182 183 simple-audio-card,cpu { 184 sound-dai = <&i2s1>; 185 }; 186 187 simple-audio-card,codec { 188 sound-dai = <&codec>; 189 }; 190 }; 191 192 arm-pmu { 193 compatible = "arm,cortex-a53-pmu"; 194 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 198 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 199 }; 200 201 display_subsystem: display-subsystem { 202 compatible = "rockchip,display-subsystem"; 203 ports = <&vop_out>; 204 }; 205 206 hdmi_sound: hdmi-sound { 207 compatible = "simple-audio-card"; 208 simple-audio-card,format = "i2s"; 209 simple-audio-card,mclk-fs = <128>; 210 simple-audio-card,name = "HDMI"; 211 status = "disabled"; 212 213 simple-audio-card,cpu { 214 sound-dai = <&i2s0>; 215 }; 216 217 simple-audio-card,codec { 218 sound-dai = <&hdmi>; 219 }; 220 }; 221 222 psci { 223 compatible = "arm,psci-1.0", "arm,psci-0.2"; 224 method = "smc"; 225 }; 226 227 timer { 228 compatible = "arm,armv8-timer"; 229 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 231 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 232 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 233 }; 234 235 xin24m: xin24m { 236 compatible = "fixed-clock"; 237 #clock-cells = <0>; 238 clock-frequency = <24000000>; 239 clock-output-names = "xin24m"; 240 }; 241 242 i2s0: i2s@ff000000 { 243 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 244 reg = <0x0 0xff000000 0x0 0x1000>; 245 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 247 clock-names = "i2s_clk", "i2s_hclk"; 248 dmas = <&dmac 11>, <&dmac 12>; 249 dma-names = "tx", "rx"; 250 #sound-dai-cells = <0>; 251 status = "disabled"; 252 }; 253 254 i2s1: i2s@ff010000 { 255 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 256 reg = <0x0 0xff010000 0x0 0x1000>; 257 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 259 clock-names = "i2s_clk", "i2s_hclk"; 260 dmas = <&dmac 14>, <&dmac 15>; 261 dma-names = "tx", "rx"; 262 #sound-dai-cells = <0>; 263 status = "disabled"; 264 }; 265 266 i2s2: i2s@ff020000 { 267 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 268 reg = <0x0 0xff020000 0x0 0x1000>; 269 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 271 clock-names = "i2s_clk", "i2s_hclk"; 272 dmas = <&dmac 0>, <&dmac 1>; 273 dma-names = "tx", "rx"; 274 #sound-dai-cells = <0>; 275 status = "disabled"; 276 }; 277 278 spdif: spdif@ff030000 { 279 compatible = "rockchip,rk3328-spdif"; 280 reg = <0x0 0xff030000 0x0 0x1000>; 281 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 283 clock-names = "mclk", "hclk"; 284 dmas = <&dmac 10>; 285 dma-names = "tx"; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&spdifm2_tx>; 288 #sound-dai-cells = <0>; 289 status = "disabled"; 290 }; 291 292 pdm: pdm@ff040000 { 293 compatible = "rockchip,pdm"; 294 reg = <0x0 0xff040000 0x0 0x1000>; 295 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 296 clock-names = "pdm_clk", "pdm_hclk"; 297 dmas = <&dmac 16>; 298 dma-names = "rx"; 299 pinctrl-names = "default", "sleep"; 300 pinctrl-0 = <&pdmm0_clk 301 &pdmm0_sdi0 302 &pdmm0_sdi1 303 &pdmm0_sdi2 304 &pdmm0_sdi3>; 305 pinctrl-1 = <&pdmm0_clk_sleep 306 &pdmm0_sdi0_sleep 307 &pdmm0_sdi1_sleep 308 &pdmm0_sdi2_sleep 309 &pdmm0_sdi3_sleep>; 310 status = "disabled"; 311 }; 312 313 grf: syscon@ff100000 { 314 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 315 reg = <0x0 0xff100000 0x0 0x1000>; 316 317 io_domains: io-domains { 318 compatible = "rockchip,rk3328-io-voltage-domain"; 319 status = "disabled"; 320 }; 321 322 grf_gpio: gpio { 323 compatible = "rockchip,rk3328-grf-gpio"; 324 gpio-controller; 325 #gpio-cells = <2>; 326 }; 327 328 power: power-controller { 329 compatible = "rockchip,rk3328-power-controller"; 330 #power-domain-cells = <1>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 power-domain@RK3328_PD_HEVC { 335 reg = <RK3328_PD_HEVC>; 336 #power-domain-cells = <0>; 337 }; 338 power-domain@RK3328_PD_VIDEO { 339 reg = <RK3328_PD_VIDEO>; 340 clocks = <&cru ACLK_RKVDEC>, 341 <&cru HCLK_RKVDEC>, 342 <&cru SCLK_VDEC_CABAC>, 343 <&cru SCLK_VDEC_CORE>; 344 #power-domain-cells = <0>; 345 }; 346 power-domain@RK3328_PD_VPU { 347 reg = <RK3328_PD_VPU>; 348 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 349 #power-domain-cells = <0>; 350 }; 351 }; 352 353 reboot-mode { 354 compatible = "syscon-reboot-mode"; 355 offset = <0x5c8>; 356 mode-normal = <BOOT_NORMAL>; 357 mode-recovery = <BOOT_RECOVERY>; 358 mode-bootloader = <BOOT_FASTBOOT>; 359 mode-loader = <BOOT_BL_DOWNLOAD>; 360 }; 361 }; 362 363 uart0: serial@ff110000 { 364 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 365 reg = <0x0 0xff110000 0x0 0x100>; 366 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 368 clock-names = "baudclk", "apb_pclk"; 369 dmas = <&dmac 2>, <&dmac 3>; 370 dma-names = "tx", "rx"; 371 pinctrl-names = "default"; 372 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 373 reg-io-width = <4>; 374 reg-shift = <2>; 375 status = "disabled"; 376 }; 377 378 uart1: serial@ff120000 { 379 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 380 reg = <0x0 0xff120000 0x0 0x100>; 381 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 383 clock-names = "baudclk", "apb_pclk"; 384 dmas = <&dmac 4>, <&dmac 5>; 385 dma-names = "tx", "rx"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 388 reg-io-width = <4>; 389 reg-shift = <2>; 390 status = "disabled"; 391 }; 392 393 uart2: serial@ff130000 { 394 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 395 reg = <0x0 0xff130000 0x0 0x100>; 396 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 398 clock-names = "baudclk", "apb_pclk"; 399 dmas = <&dmac 6>, <&dmac 7>; 400 dma-names = "tx", "rx"; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&uart2m1_xfer>; 403 reg-io-width = <4>; 404 reg-shift = <2>; 405 status = "disabled"; 406 }; 407 408 i2c0: i2c@ff150000 { 409 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 410 reg = <0x0 0xff150000 0x0 0x1000>; 411 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 415 clock-names = "i2c", "pclk"; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&i2c0_xfer>; 418 status = "disabled"; 419 }; 420 421 i2c1: i2c@ff160000 { 422 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 423 reg = <0x0 0xff160000 0x0 0x1000>; 424 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 428 clock-names = "i2c", "pclk"; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&i2c1_xfer>; 431 status = "disabled"; 432 }; 433 434 i2c2: i2c@ff170000 { 435 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 436 reg = <0x0 0xff170000 0x0 0x1000>; 437 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 441 clock-names = "i2c", "pclk"; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&i2c2_xfer>; 444 status = "disabled"; 445 }; 446 447 i2c3: i2c@ff180000 { 448 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 449 reg = <0x0 0xff180000 0x0 0x1000>; 450 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 454 clock-names = "i2c", "pclk"; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&i2c3_xfer>; 457 status = "disabled"; 458 }; 459 460 spi0: spi@ff190000 { 461 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 462 reg = <0x0 0xff190000 0x0 0x1000>; 463 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 467 clock-names = "spiclk", "apb_pclk"; 468 dmas = <&dmac 8>, <&dmac 9>; 469 dma-names = "tx", "rx"; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 472 status = "disabled"; 473 }; 474 475 wdt: watchdog@ff1a0000 { 476 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 477 reg = <0x0 0xff1a0000 0x0 0x100>; 478 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cru PCLK_WDT>; 480 }; 481 482 pwm0: pwm@ff1b0000 { 483 compatible = "rockchip,rk3328-pwm"; 484 reg = <0x0 0xff1b0000 0x0 0x10>; 485 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 486 clock-names = "pwm", "pclk"; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&pwm0_pin>; 489 #pwm-cells = <3>; 490 status = "disabled"; 491 }; 492 493 pwm1: pwm@ff1b0010 { 494 compatible = "rockchip,rk3328-pwm"; 495 reg = <0x0 0xff1b0010 0x0 0x10>; 496 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 497 clock-names = "pwm", "pclk"; 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pwm1_pin>; 500 #pwm-cells = <3>; 501 status = "disabled"; 502 }; 503 504 pwm2: pwm@ff1b0020 { 505 compatible = "rockchip,rk3328-pwm"; 506 reg = <0x0 0xff1b0020 0x0 0x10>; 507 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 508 clock-names = "pwm", "pclk"; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&pwm2_pin>; 511 #pwm-cells = <3>; 512 status = "disabled"; 513 }; 514 515 pwm3: pwm@ff1b0030 { 516 compatible = "rockchip,rk3328-pwm"; 517 reg = <0x0 0xff1b0030 0x0 0x10>; 518 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 519 clock-names = "pwm", "pclk"; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&pwmir_pin>; 522 #pwm-cells = <3>; 523 status = "disabled"; 524 }; 525 526 dmac: dma-controller@ff1f0000 { 527 compatible = "arm,pl330", "arm,primecell"; 528 reg = <0x0 0xff1f0000 0x0 0x4000>; 529 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 531 arm,pl330-periph-burst; 532 clocks = <&cru ACLK_DMAC>; 533 clock-names = "apb_pclk"; 534 #dma-cells = <1>; 535 }; 536 537 thermal-zones { 538 soc_thermal: soc-thermal { 539 polling-delay-passive = <20>; 540 polling-delay = <1000>; 541 sustainable-power = <1000>; 542 543 thermal-sensors = <&tsadc 0>; 544 545 trips { 546 threshold: trip-point0 { 547 temperature = <70000>; 548 hysteresis = <2000>; 549 type = "passive"; 550 }; 551 target: trip-point1 { 552 temperature = <85000>; 553 hysteresis = <2000>; 554 type = "passive"; 555 }; 556 soc_crit: soc-crit { 557 temperature = <95000>; 558 hysteresis = <2000>; 559 type = "critical"; 560 }; 561 }; 562 563 cooling-maps { 564 map0 { 565 trip = <&target>; 566 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 567 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 568 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 569 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 570 contribution = <4096>; 571 }; 572 }; 573 }; 574 575 }; 576 577 tsadc: tsadc@ff250000 { 578 compatible = "rockchip,rk3328-tsadc"; 579 reg = <0x0 0xff250000 0x0 0x100>; 580 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 581 assigned-clocks = <&cru SCLK_TSADC>; 582 assigned-clock-rates = <50000>; 583 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 584 clock-names = "tsadc", "apb_pclk"; 585 pinctrl-names = "init", "default", "sleep"; 586 pinctrl-0 = <&otp_pin>; 587 pinctrl-1 = <&otp_out>; 588 pinctrl-2 = <&otp_pin>; 589 resets = <&cru SRST_TSADC>; 590 reset-names = "tsadc-apb"; 591 rockchip,grf = <&grf>; 592 rockchip,hw-tshut-temp = <100000>; 593 #thermal-sensor-cells = <1>; 594 status = "disabled"; 595 }; 596 597 efuse: efuse@ff260000 { 598 compatible = "rockchip,rk3328-efuse"; 599 reg = <0x0 0xff260000 0x0 0x50>; 600 #address-cells = <1>; 601 #size-cells = <1>; 602 clocks = <&cru SCLK_EFUSE>; 603 clock-names = "pclk_efuse"; 604 rockchip,efuse-size = <0x20>; 605 606 /* Data cells */ 607 efuse_id: id@7 { 608 reg = <0x07 0x10>; 609 }; 610 cpu_leakage: cpu-leakage@17 { 611 reg = <0x17 0x1>; 612 }; 613 logic_leakage: logic-leakage@19 { 614 reg = <0x19 0x1>; 615 }; 616 efuse_cpu_version: cpu-version@1a { 617 reg = <0x1a 0x1>; 618 bits = <3 3>; 619 }; 620 }; 621 622 saradc: adc@ff280000 { 623 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 624 reg = <0x0 0xff280000 0x0 0x100>; 625 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 626 #io-channel-cells = <1>; 627 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 628 clock-names = "saradc", "apb_pclk"; 629 resets = <&cru SRST_SARADC_P>; 630 reset-names = "saradc-apb"; 631 status = "disabled"; 632 }; 633 634 gpu: gpu@ff300000 { 635 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 636 reg = <0x0 0xff300000 0x0 0x30000>; 637 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-names = "gp", 645 "gpmmu", 646 "pp", 647 "pp0", 648 "ppmmu0", 649 "pp1", 650 "ppmmu1"; 651 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 652 clock-names = "bus", "core"; 653 resets = <&cru SRST_GPU_A>; 654 }; 655 656 h265e_mmu: iommu@ff330200 { 657 compatible = "rockchip,iommu"; 658 reg = <0x0 0xff330200 0 0x100>; 659 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 661 clock-names = "aclk", "iface"; 662 #iommu-cells = <0>; 663 status = "disabled"; 664 }; 665 666 vepu_mmu: iommu@ff340800 { 667 compatible = "rockchip,iommu"; 668 reg = <0x0 0xff340800 0x0 0x40>; 669 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 671 clock-names = "aclk", "iface"; 672 #iommu-cells = <0>; 673 status = "disabled"; 674 }; 675 676 vpu: video-codec@ff350000 { 677 compatible = "rockchip,rk3328-vpu"; 678 reg = <0x0 0xff350000 0x0 0x800>; 679 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 680 interrupt-names = "vdpu"; 681 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 682 clock-names = "aclk", "hclk"; 683 iommus = <&vpu_mmu>; 684 power-domains = <&power RK3328_PD_VPU>; 685 }; 686 687 vpu_mmu: iommu@ff350800 { 688 compatible = "rockchip,iommu"; 689 reg = <0x0 0xff350800 0x0 0x40>; 690 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 692 clock-names = "aclk", "iface"; 693 #iommu-cells = <0>; 694 power-domains = <&power RK3328_PD_VPU>; 695 }; 696 697 vdec: video-codec@ff360000 { 698 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 699 reg = <0x0 0xff360000 0x0 0x480>; 700 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 702 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 703 clock-names = "axi", "ahb", "cabac", "core"; 704 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 705 <&cru SCLK_VDEC_CORE>; 706 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 707 iommus = <&vdec_mmu>; 708 power-domains = <&power RK3328_PD_VIDEO>; 709 }; 710 711 vdec_mmu: iommu@ff360480 { 712 compatible = "rockchip,iommu"; 713 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 714 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 716 clock-names = "aclk", "iface"; 717 #iommu-cells = <0>; 718 power-domains = <&power RK3328_PD_VIDEO>; 719 }; 720 721 vop: vop@ff370000 { 722 compatible = "rockchip,rk3328-vop"; 723 reg = <0x0 0xff370000 0x0 0x3efc>; 724 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 725 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 726 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 727 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 728 reset-names = "axi", "ahb", "dclk"; 729 iommus = <&vop_mmu>; 730 status = "disabled"; 731 732 vop_out: port { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 736 vop_out_hdmi: endpoint@0 { 737 reg = <0>; 738 remote-endpoint = <&hdmi_in_vop>; 739 }; 740 }; 741 }; 742 743 vop_mmu: iommu@ff373f00 { 744 compatible = "rockchip,iommu"; 745 reg = <0x0 0xff373f00 0x0 0x100>; 746 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 748 clock-names = "aclk", "iface"; 749 #iommu-cells = <0>; 750 status = "disabled"; 751 }; 752 753 hdmi: hdmi@ff3c0000 { 754 compatible = "rockchip,rk3328-dw-hdmi"; 755 reg = <0x0 0xff3c0000 0x0 0x20000>; 756 reg-io-width = <4>; 757 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cru PCLK_HDMI>, 759 <&cru SCLK_HDMI_SFC>, 760 <&cru SCLK_RTC32K>; 761 clock-names = "iahb", 762 "isfr", 763 "cec"; 764 phys = <&hdmiphy>; 765 phy-names = "hdmi"; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 768 rockchip,grf = <&grf>; 769 #sound-dai-cells = <0>; 770 status = "disabled"; 771 772 ports { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 776 hdmi_in: port@0 { 777 reg = <0>; 778 779 hdmi_in_vop: endpoint { 780 remote-endpoint = <&vop_out_hdmi>; 781 }; 782 }; 783 784 hdmi_out: port@1 { 785 reg = <1>; 786 }; 787 }; 788 }; 789 790 codec: codec@ff410000 { 791 compatible = "rockchip,rk3328-codec"; 792 reg = <0x0 0xff410000 0x0 0x1000>; 793 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 794 clock-names = "pclk", "mclk"; 795 rockchip,grf = <&grf>; 796 #sound-dai-cells = <0>; 797 status = "disabled"; 798 }; 799 800 hdmiphy: phy@ff430000 { 801 compatible = "rockchip,rk3328-hdmi-phy"; 802 reg = <0x0 0xff430000 0x0 0x10000>; 803 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 805 clock-names = "sysclk", "refoclk", "refpclk"; 806 clock-output-names = "hdmi_phy"; 807 #clock-cells = <0>; 808 nvmem-cells = <&efuse_cpu_version>; 809 nvmem-cell-names = "cpu-version"; 810 #phy-cells = <0>; 811 status = "disabled"; 812 }; 813 814 cru: clock-controller@ff440000 { 815 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 816 reg = <0x0 0xff440000 0x0 0x1000>; 817 rockchip,grf = <&grf>; 818 #clock-cells = <1>; 819 #reset-cells = <1>; 820 assigned-clocks = 821 /* 822 * CPLL should run at 1200, but that is to high for 823 * the initial dividers of most of its children. 824 * We need set cpll child clk div first, 825 * and then set the cpll frequency. 826 */ 827 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 828 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 829 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 830 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 831 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 832 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 833 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 834 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 835 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 836 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 837 <&cru SCLK_WIFI>, <&cru ARMCLK>, 838 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 839 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 840 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 841 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 842 <&cru SCLK_RTC32K>; 843 assigned-clock-parents = 844 <&cru HDMIPHY>, <&cru PLL_APLL>, 845 <&cru PLL_GPLL>, <&xin24m>, 846 <&xin24m>, <&xin24m>; 847 assigned-clock-rates = 848 <0>, <61440000>, 849 <0>, <24000000>, 850 <24000000>, <24000000>, 851 <15000000>, <15000000>, 852 <300000000>, <100000000>, 853 <400000000>, <100000000>, 854 <50000000>, <100000000>, 855 <100000000>, <100000000>, 856 <50000000>, <50000000>, 857 <50000000>, <50000000>, 858 <24000000>, <600000000>, 859 <491520000>, <1200000000>, 860 <150000000>, <75000000>, 861 <75000000>, <150000000>, 862 <75000000>, <75000000>, 863 <32768>; 864 }; 865 866 usb2phy_grf: syscon@ff450000 { 867 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 868 "simple-mfd"; 869 reg = <0x0 0xff450000 0x0 0x10000>; 870 #address-cells = <1>; 871 #size-cells = <1>; 872 873 u2phy: usb2phy@100 { 874 compatible = "rockchip,rk3328-usb2phy"; 875 reg = <0x100 0x10>; 876 clocks = <&xin24m>; 877 clock-names = "phyclk"; 878 clock-output-names = "usb480m_phy"; 879 #clock-cells = <0>; 880 assigned-clocks = <&cru USB480M>; 881 assigned-clock-parents = <&u2phy>; 882 status = "disabled"; 883 884 u2phy_otg: otg-port { 885 #phy-cells = <0>; 886 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 889 interrupt-names = "otg-bvalid", "otg-id", 890 "linestate"; 891 status = "disabled"; 892 }; 893 894 u2phy_host: host-port { 895 #phy-cells = <0>; 896 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 897 interrupt-names = "linestate"; 898 status = "disabled"; 899 }; 900 }; 901 }; 902 903 sdmmc: mmc@ff500000 { 904 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 905 reg = <0x0 0xff500000 0x0 0x4000>; 906 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 908 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 909 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 910 fifo-depth = <0x100>; 911 max-frequency = <150000000>; 912 resets = <&cru SRST_MMC0>; 913 reset-names = "reset"; 914 status = "disabled"; 915 }; 916 917 sdio: mmc@ff510000 { 918 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 919 reg = <0x0 0xff510000 0x0 0x4000>; 920 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 922 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 923 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 924 fifo-depth = <0x100>; 925 max-frequency = <150000000>; 926 resets = <&cru SRST_SDIO>; 927 reset-names = "reset"; 928 status = "disabled"; 929 }; 930 931 emmc: mmc@ff520000 { 932 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 933 reg = <0x0 0xff520000 0x0 0x4000>; 934 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 936 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 937 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 938 fifo-depth = <0x100>; 939 max-frequency = <150000000>; 940 resets = <&cru SRST_EMMC>; 941 reset-names = "reset"; 942 status = "disabled"; 943 }; 944 945 gmac2io: ethernet@ff540000 { 946 compatible = "rockchip,rk3328-gmac"; 947 reg = <0x0 0xff540000 0x0 0x10000>; 948 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "macirq"; 950 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 951 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 952 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 953 <&cru PCLK_MAC2IO>; 954 clock-names = "stmmaceth", "mac_clk_rx", 955 "mac_clk_tx", "clk_mac_ref", 956 "clk_mac_refout", "aclk_mac", 957 "pclk_mac"; 958 resets = <&cru SRST_GMAC2IO_A>; 959 reset-names = "stmmaceth"; 960 rockchip,grf = <&grf>; 961 tx-fifo-depth = <2048>; 962 rx-fifo-depth = <4096>; 963 snps,txpbl = <0x4>; 964 status = "disabled"; 965 }; 966 967 gmac2phy: ethernet@ff550000 { 968 compatible = "rockchip,rk3328-gmac"; 969 reg = <0x0 0xff550000 0x0 0x10000>; 970 rockchip,grf = <&grf>; 971 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 972 interrupt-names = "macirq"; 973 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 974 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 975 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 976 <&cru SCLK_MAC2PHY_OUT>; 977 clock-names = "stmmaceth", "mac_clk_rx", 978 "mac_clk_tx", "clk_mac_ref", 979 "aclk_mac", "pclk_mac", 980 "clk_macphy"; 981 resets = <&cru SRST_GMAC2PHY_A>; 982 reset-names = "stmmaceth"; 983 phy-mode = "rmii"; 984 phy-handle = <&phy>; 985 tx-fifo-depth = <2048>; 986 rx-fifo-depth = <4096>; 987 snps,txpbl = <0x4>; 988 clock_in_out = "output"; 989 status = "disabled"; 990 991 mdio { 992 compatible = "snps,dwmac-mdio"; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 996 phy: ethernet-phy@0 { 997 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 998 reg = <0>; 999 clocks = <&cru SCLK_MAC2PHY_OUT>; 1000 resets = <&cru SRST_MACPHY>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 1003 phy-is-integrated; 1004 }; 1005 }; 1006 }; 1007 1008 usb20_otg: usb@ff580000 { 1009 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 1010 "snps,dwc2"; 1011 reg = <0x0 0xff580000 0x0 0x40000>; 1012 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&cru HCLK_OTG>; 1014 clock-names = "otg"; 1015 dr_mode = "otg"; 1016 g-np-tx-fifo-size = <16>; 1017 g-rx-fifo-size = <280>; 1018 g-tx-fifo-size = <256 128 128 64 32 16>; 1019 phys = <&u2phy_otg>; 1020 phy-names = "usb2-phy"; 1021 status = "disabled"; 1022 }; 1023 1024 usb_host0_ehci: usb@ff5c0000 { 1025 compatible = "generic-ehci"; 1026 reg = <0x0 0xff5c0000 0x0 0x10000>; 1027 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1029 phys = <&u2phy_host>; 1030 phy-names = "usb"; 1031 status = "disabled"; 1032 }; 1033 1034 usb_host0_ohci: usb@ff5d0000 { 1035 compatible = "generic-ohci"; 1036 reg = <0x0 0xff5d0000 0x0 0x10000>; 1037 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&cru HCLK_HOST0>, <&u2phy>; 1039 phys = <&u2phy_host>; 1040 phy-names = "usb"; 1041 status = "disabled"; 1042 }; 1043 1044 sdmmc_ext: mmc@ff5f0000 { 1045 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 1046 reg = <0x0 0xff5f0000 0x0 0x4000>; 1047 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, 1049 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; 1050 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1051 fifo-depth = <0x100>; 1052 max-frequency = <150000000>; 1053 resets = <&cru SRST_SDMMCEXT>; 1054 reset-names = "reset"; 1055 status = "disabled"; 1056 }; 1057 1058 usbdrd3: usb@ff600000 { 1059 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 1060 reg = <0x0 0xff600000 0x0 0x100000>; 1061 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1063 <&cru ACLK_USB3OTG>; 1064 clock-names = "ref_clk", "suspend_clk", 1065 "bus_clk"; 1066 dr_mode = "otg"; 1067 phy_type = "utmi_wide"; 1068 snps,dis-del-phy-power-chg-quirk; 1069 snps,dis_enblslpm_quirk; 1070 snps,dis-tx-ipgap-linecheck-quirk; 1071 snps,dis-u2-freeclk-exists-quirk; 1072 snps,dis_u2_susphy_quirk; 1073 snps,dis_u3_susphy_quirk; 1074 status = "disabled"; 1075 }; 1076 1077 gic: interrupt-controller@ff811000 { 1078 compatible = "arm,gic-400"; 1079 #interrupt-cells = <3>; 1080 #address-cells = <0>; 1081 interrupt-controller; 1082 reg = <0x0 0xff811000 0 0x1000>, 1083 <0x0 0xff812000 0 0x2000>, 1084 <0x0 0xff814000 0 0x2000>, 1085 <0x0 0xff816000 0 0x2000>; 1086 interrupts = <GIC_PPI 9 1087 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1088 }; 1089 1090 crypto: crypto@ff060000 { 1091 compatible = "rockchip,rk3328-crypto"; 1092 reg = <0x0 0xff060000 0x0 0x4000>; 1093 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&cru HCLK_CRYPTO_MST>, <&cru HCLK_CRYPTO_SLV>, 1095 <&cru SCLK_CRYPTO>; 1096 clock-names = "hclk_master", "hclk_slave", "sclk"; 1097 resets = <&cru SRST_CRYPTO>; 1098 reset-names = "crypto-rst"; 1099 }; 1100 1101 pinctrl: pinctrl { 1102 compatible = "rockchip,rk3328-pinctrl"; 1103 rockchip,grf = <&grf>; 1104 #address-cells = <2>; 1105 #size-cells = <2>; 1106 ranges; 1107 1108 gpio0: gpio@ff210000 { 1109 compatible = "rockchip,gpio-bank"; 1110 reg = <0x0 0xff210000 0x0 0x100>; 1111 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&cru PCLK_GPIO0>; 1113 1114 gpio-controller; 1115 #gpio-cells = <2>; 1116 1117 interrupt-controller; 1118 #interrupt-cells = <2>; 1119 }; 1120 1121 gpio1: gpio@ff220000 { 1122 compatible = "rockchip,gpio-bank"; 1123 reg = <0x0 0xff220000 0x0 0x100>; 1124 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&cru PCLK_GPIO1>; 1126 1127 gpio-controller; 1128 #gpio-cells = <2>; 1129 1130 interrupt-controller; 1131 #interrupt-cells = <2>; 1132 }; 1133 1134 gpio2: gpio@ff230000 { 1135 compatible = "rockchip,gpio-bank"; 1136 reg = <0x0 0xff230000 0x0 0x100>; 1137 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1138 clocks = <&cru PCLK_GPIO2>; 1139 1140 gpio-controller; 1141 #gpio-cells = <2>; 1142 1143 interrupt-controller; 1144 #interrupt-cells = <2>; 1145 }; 1146 1147 gpio3: gpio@ff240000 { 1148 compatible = "rockchip,gpio-bank"; 1149 reg = <0x0 0xff240000 0x0 0x100>; 1150 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&cru PCLK_GPIO3>; 1152 1153 gpio-controller; 1154 #gpio-cells = <2>; 1155 1156 interrupt-controller; 1157 #interrupt-cells = <2>; 1158 }; 1159 1160 pcfg_pull_up: pcfg-pull-up { 1161 bias-pull-up; 1162 }; 1163 1164 pcfg_pull_down: pcfg-pull-down { 1165 bias-pull-down; 1166 }; 1167 1168 pcfg_pull_none: pcfg-pull-none { 1169 bias-disable; 1170 }; 1171 1172 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1173 bias-disable; 1174 drive-strength = <2>; 1175 }; 1176 1177 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1178 bias-pull-up; 1179 drive-strength = <2>; 1180 }; 1181 1182 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1183 bias-pull-up; 1184 drive-strength = <4>; 1185 }; 1186 1187 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1188 bias-disable; 1189 drive-strength = <4>; 1190 }; 1191 1192 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1193 bias-pull-down; 1194 drive-strength = <4>; 1195 }; 1196 1197 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1198 bias-disable; 1199 drive-strength = <8>; 1200 }; 1201 1202 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1203 bias-pull-up; 1204 drive-strength = <8>; 1205 }; 1206 1207 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1208 bias-disable; 1209 drive-strength = <12>; 1210 }; 1211 1212 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1213 bias-pull-up; 1214 drive-strength = <12>; 1215 }; 1216 1217 pcfg_output_high: pcfg-output-high { 1218 output-high; 1219 }; 1220 1221 pcfg_output_low: pcfg-output-low { 1222 output-low; 1223 }; 1224 1225 pcfg_input_high: pcfg-input-high { 1226 bias-pull-up; 1227 input-enable; 1228 }; 1229 1230 pcfg_input: pcfg-input { 1231 input-enable; 1232 }; 1233 1234 i2c0 { 1235 i2c0_xfer: i2c0-xfer { 1236 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1237 <2 RK_PD1 1 &pcfg_pull_none>; 1238 }; 1239 }; 1240 1241 i2c1 { 1242 i2c1_xfer: i2c1-xfer { 1243 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1244 <2 RK_PA5 2 &pcfg_pull_none>; 1245 }; 1246 }; 1247 1248 i2c2 { 1249 i2c2_xfer: i2c2-xfer { 1250 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1251 <2 RK_PB6 1 &pcfg_pull_none>; 1252 }; 1253 }; 1254 1255 i2c3 { 1256 i2c3_xfer: i2c3-xfer { 1257 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1258 <0 RK_PA6 2 &pcfg_pull_none>; 1259 }; 1260 i2c3_pins: i2c3-pins { 1261 rockchip,pins = 1262 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1263 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1264 }; 1265 }; 1266 1267 hdmi_i2c { 1268 hdmii2c_xfer: hdmii2c-xfer { 1269 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1270 <0 RK_PA6 1 &pcfg_pull_none>; 1271 }; 1272 }; 1273 1274 pdm-0 { 1275 pdmm0_clk: pdmm0-clk { 1276 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1277 }; 1278 1279 pdmm0_fsync: pdmm0-fsync { 1280 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1281 }; 1282 1283 pdmm0_sdi0: pdmm0-sdi0 { 1284 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1285 }; 1286 1287 pdmm0_sdi1: pdmm0-sdi1 { 1288 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1289 }; 1290 1291 pdmm0_sdi2: pdmm0-sdi2 { 1292 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1293 }; 1294 1295 pdmm0_sdi3: pdmm0-sdi3 { 1296 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1297 }; 1298 1299 pdmm0_clk_sleep: pdmm0-clk-sleep { 1300 rockchip,pins = 1301 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1302 }; 1303 1304 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1305 rockchip,pins = 1306 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1307 }; 1308 1309 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1310 rockchip,pins = 1311 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1312 }; 1313 1314 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1315 rockchip,pins = 1316 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1317 }; 1318 1319 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1320 rockchip,pins = 1321 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1322 }; 1323 1324 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1325 rockchip,pins = 1326 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1327 }; 1328 }; 1329 1330 tsadc { 1331 otp_pin: otp-pin { 1332 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1333 }; 1334 1335 otp_out: otp-out { 1336 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1337 }; 1338 }; 1339 1340 uart0 { 1341 uart0_xfer: uart0-xfer { 1342 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1343 <1 RK_PB0 1 &pcfg_pull_up>; 1344 }; 1345 1346 uart0_cts: uart0-cts { 1347 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1348 }; 1349 1350 uart0_rts: uart0-rts { 1351 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1352 }; 1353 1354 uart0_rts_pin: uart0-rts-pin { 1355 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1356 }; 1357 }; 1358 1359 uart1 { 1360 uart1_xfer: uart1-xfer { 1361 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1362 <3 RK_PA6 4 &pcfg_pull_up>; 1363 }; 1364 1365 uart1_cts: uart1-cts { 1366 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1367 }; 1368 1369 uart1_rts: uart1-rts { 1370 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1371 }; 1372 1373 uart1_rts_pin: uart1-rts-pin { 1374 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1375 }; 1376 }; 1377 1378 uart2-0 { 1379 uart2m0_xfer: uart2m0-xfer { 1380 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1381 <1 RK_PA1 2 &pcfg_pull_up>; 1382 }; 1383 }; 1384 1385 uart2-1 { 1386 uart2m1_xfer: uart2m1-xfer { 1387 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1388 <2 RK_PA1 1 &pcfg_pull_up>; 1389 }; 1390 }; 1391 1392 spi0-0 { 1393 spi0m0_clk: spi0m0-clk { 1394 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1395 }; 1396 1397 spi0m0_cs0: spi0m0-cs0 { 1398 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1399 }; 1400 1401 spi0m0_tx: spi0m0-tx { 1402 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1403 }; 1404 1405 spi0m0_rx: spi0m0-rx { 1406 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1407 }; 1408 1409 spi0m0_cs1: spi0m0-cs1 { 1410 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1411 }; 1412 }; 1413 1414 spi0-1 { 1415 spi0m1_clk: spi0m1-clk { 1416 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1417 }; 1418 1419 spi0m1_cs0: spi0m1-cs0 { 1420 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1421 }; 1422 1423 spi0m1_tx: spi0m1-tx { 1424 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1425 }; 1426 1427 spi0m1_rx: spi0m1-rx { 1428 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1429 }; 1430 1431 spi0m1_cs1: spi0m1-cs1 { 1432 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1433 }; 1434 }; 1435 1436 spi0-2 { 1437 spi0m2_clk: spi0m2-clk { 1438 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1439 }; 1440 1441 spi0m2_cs0: spi0m2-cs0 { 1442 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1443 }; 1444 1445 spi0m2_tx: spi0m2-tx { 1446 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1447 }; 1448 1449 spi0m2_rx: spi0m2-rx { 1450 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1451 }; 1452 }; 1453 1454 i2s1 { 1455 i2s1_mclk: i2s1-mclk { 1456 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1457 }; 1458 1459 i2s1_sclk: i2s1-sclk { 1460 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1461 }; 1462 1463 i2s1_lrckrx: i2s1-lrckrx { 1464 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1465 }; 1466 1467 i2s1_lrcktx: i2s1-lrcktx { 1468 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1469 }; 1470 1471 i2s1_sdi: i2s1-sdi { 1472 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1473 }; 1474 1475 i2s1_sdo: i2s1-sdo { 1476 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1477 }; 1478 1479 i2s1_sdio1: i2s1-sdio1 { 1480 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1481 }; 1482 1483 i2s1_sdio2: i2s1-sdio2 { 1484 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1485 }; 1486 1487 i2s1_sdio3: i2s1-sdio3 { 1488 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1489 }; 1490 1491 i2s1_sleep: i2s1-sleep { 1492 rockchip,pins = 1493 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1494 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1495 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1496 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1497 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1498 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1499 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1500 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1501 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1502 }; 1503 }; 1504 1505 i2s2-0 { 1506 i2s2m0_mclk: i2s2m0-mclk { 1507 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1508 }; 1509 1510 i2s2m0_sclk: i2s2m0-sclk { 1511 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1512 }; 1513 1514 i2s2m0_lrckrx: i2s2m0-lrckrx { 1515 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1516 }; 1517 1518 i2s2m0_lrcktx: i2s2m0-lrcktx { 1519 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1520 }; 1521 1522 i2s2m0_sdi: i2s2m0-sdi { 1523 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1524 }; 1525 1526 i2s2m0_sdo: i2s2m0-sdo { 1527 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1528 }; 1529 1530 i2s2m0_sleep: i2s2m0-sleep { 1531 rockchip,pins = 1532 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1533 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1534 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1535 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1536 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1537 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1538 }; 1539 }; 1540 1541 i2s2-1 { 1542 i2s2m1_mclk: i2s2m1-mclk { 1543 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1544 }; 1545 1546 i2s2m1_sclk: i2s2m1-sclk { 1547 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1548 }; 1549 1550 i2s2m1_lrckrx: i2sm1-lrckrx { 1551 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1552 }; 1553 1554 i2s2m1_lrcktx: i2s2m1-lrcktx { 1555 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1556 }; 1557 1558 i2s2m1_sdi: i2s2m1-sdi { 1559 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1560 }; 1561 1562 i2s2m1_sdo: i2s2m1-sdo { 1563 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1564 }; 1565 1566 i2s2m1_sleep: i2s2m1-sleep { 1567 rockchip,pins = 1568 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1569 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1570 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1571 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1572 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1573 }; 1574 }; 1575 1576 spdif-0 { 1577 spdifm0_tx: spdifm0-tx { 1578 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1579 }; 1580 }; 1581 1582 spdif-1 { 1583 spdifm1_tx: spdifm1-tx { 1584 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1585 }; 1586 }; 1587 1588 spdif-2 { 1589 spdifm2_tx: spdifm2-tx { 1590 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1591 }; 1592 }; 1593 1594 sdmmc0-0 { 1595 sdmmc0m0_pwren: sdmmc0m0-pwren { 1596 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1597 }; 1598 1599 sdmmc0m0_pin: sdmmc0m0-pin { 1600 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1601 }; 1602 }; 1603 1604 sdmmc0-1 { 1605 sdmmc0m1_pwren: sdmmc0m1-pwren { 1606 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1607 }; 1608 1609 sdmmc0m1_pin: sdmmc0m1-pin { 1610 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1611 }; 1612 }; 1613 1614 sdmmc0 { 1615 sdmmc0_clk: sdmmc0-clk { 1616 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1617 }; 1618 1619 sdmmc0_cmd: sdmmc0-cmd { 1620 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1621 }; 1622 1623 sdmmc0_dectn: sdmmc0-dectn { 1624 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1625 }; 1626 1627 sdmmc0_wrprt: sdmmc0-wrprt { 1628 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1629 }; 1630 1631 sdmmc0_bus1: sdmmc0-bus1 { 1632 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1633 }; 1634 1635 sdmmc0_bus4: sdmmc0-bus4 { 1636 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1637 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1638 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1639 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1640 }; 1641 1642 sdmmc0_pins: sdmmc0-pins { 1643 rockchip,pins = 1644 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1645 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1646 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1647 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1648 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1649 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1650 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1651 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1652 }; 1653 }; 1654 1655 sdmmc0ext { 1656 sdmmc0ext_clk: sdmmc0ext-clk { 1657 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1658 }; 1659 1660 sdmmc0ext_cmd: sdmmc0ext-cmd { 1661 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1662 }; 1663 1664 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1665 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1666 }; 1667 1668 sdmmc0ext_dectn: sdmmc0ext-dectn { 1669 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1670 }; 1671 1672 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1673 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1674 }; 1675 1676 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1677 rockchip,pins = 1678 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1679 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1680 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1681 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1682 }; 1683 1684 sdmmc0ext_pins: sdmmc0ext-pins { 1685 rockchip,pins = 1686 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1687 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1688 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1689 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1690 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1691 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1692 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1693 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1694 }; 1695 }; 1696 1697 sdmmc1 { 1698 sdmmc1_clk: sdmmc1-clk { 1699 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1700 }; 1701 1702 sdmmc1_cmd: sdmmc1-cmd { 1703 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1704 }; 1705 1706 sdmmc1_pwren: sdmmc1-pwren { 1707 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1708 }; 1709 1710 sdmmc1_wrprt: sdmmc1-wrprt { 1711 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1712 }; 1713 1714 sdmmc1_dectn: sdmmc1-dectn { 1715 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1716 }; 1717 1718 sdmmc1_bus1: sdmmc1-bus1 { 1719 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1720 }; 1721 1722 sdmmc1_bus4: sdmmc1-bus4 { 1723 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1724 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1725 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1726 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1727 }; 1728 1729 sdmmc1_pins: sdmmc1-pins { 1730 rockchip,pins = 1731 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1732 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1733 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1734 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1735 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1736 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1737 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1738 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1739 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1740 }; 1741 }; 1742 1743 emmc { 1744 emmc_clk: emmc-clk { 1745 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1746 }; 1747 1748 emmc_cmd: emmc-cmd { 1749 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1750 }; 1751 1752 emmc_pwren: emmc-pwren { 1753 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1754 }; 1755 1756 emmc_rstnout: emmc-rstnout { 1757 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1758 }; 1759 1760 emmc_bus1: emmc-bus1 { 1761 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1762 }; 1763 1764 emmc_bus4: emmc-bus4 { 1765 rockchip,pins = 1766 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1767 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1768 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1769 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1770 }; 1771 1772 emmc_bus8: emmc-bus8 { 1773 rockchip,pins = 1774 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1775 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1776 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1777 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1778 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1779 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1780 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1781 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1782 }; 1783 }; 1784 1785 pwm0 { 1786 pwm0_pin: pwm0-pin { 1787 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1788 }; 1789 }; 1790 1791 pwm1 { 1792 pwm1_pin: pwm1-pin { 1793 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1794 }; 1795 }; 1796 1797 pwm2 { 1798 pwm2_pin: pwm2-pin { 1799 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1800 }; 1801 }; 1802 1803 pwmir { 1804 pwmir_pin: pwmir-pin { 1805 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1806 }; 1807 }; 1808 1809 gmac-1 { 1810 rgmiim1_pins: rgmiim1-pins { 1811 rockchip,pins = 1812 /* mac_txclk */ 1813 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1814 /* mac_rxclk */ 1815 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1816 /* mac_mdio */ 1817 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1818 /* mac_txen */ 1819 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1820 /* mac_clk */ 1821 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1822 /* mac_rxdv */ 1823 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1824 /* mac_mdc */ 1825 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1826 /* mac_rxd1 */ 1827 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1828 /* mac_rxd0 */ 1829 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1830 /* mac_txd1 */ 1831 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1832 /* mac_txd0 */ 1833 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1834 /* mac_rxd3 */ 1835 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1836 /* mac_rxd2 */ 1837 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1838 /* mac_txd3 */ 1839 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1840 /* mac_txd2 */ 1841 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1842 1843 /* mac_txclk */ 1844 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1845 /* mac_txen */ 1846 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1847 /* mac_clk */ 1848 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1849 /* mac_txd1 */ 1850 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1851 /* mac_txd0 */ 1852 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1853 /* mac_txd3 */ 1854 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1855 /* mac_txd2 */ 1856 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1857 }; 1858 1859 rmiim1_pins: rmiim1-pins { 1860 rockchip,pins = 1861 /* mac_mdio */ 1862 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1863 /* mac_txen */ 1864 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1865 /* mac_clk */ 1866 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1867 /* mac_rxer */ 1868 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1869 /* mac_rxdv */ 1870 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1871 /* mac_mdc */ 1872 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1873 /* mac_rxd1 */ 1874 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1875 /* mac_rxd0 */ 1876 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1877 /* mac_txd1 */ 1878 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1879 /* mac_txd0 */ 1880 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1881 1882 /* mac_mdio */ 1883 <0 RK_PB3 1 &pcfg_pull_none>, 1884 /* mac_txen */ 1885 <0 RK_PB4 1 &pcfg_pull_none>, 1886 /* mac_clk */ 1887 <0 RK_PD0 1 &pcfg_pull_none>, 1888 /* mac_mdc */ 1889 <0 RK_PC3 1 &pcfg_pull_none>, 1890 /* mac_txd1 */ 1891 <0 RK_PC0 1 &pcfg_pull_none>, 1892 /* mac_txd0 */ 1893 <0 RK_PC1 1 &pcfg_pull_none>; 1894 }; 1895 }; 1896 1897 gmac2phy { 1898 fephyled_speed10: fephyled-speed10 { 1899 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1900 }; 1901 1902 fephyled_duplex: fephyled-duplex { 1903 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1904 }; 1905 1906 fephyled_rxm1: fephyled-rxm1 { 1907 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1908 }; 1909 1910 fephyled_txm1: fephyled-txm1 { 1911 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1912 }; 1913 1914 fephyled_linkm1: fephyled-linkm1 { 1915 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1916 }; 1917 }; 1918 1919 tsadc_pin { 1920 tsadc_int: tsadc-int { 1921 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1922 }; 1923 tsadc_pin: tsadc-pin { 1924 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1925 }; 1926 }; 1927 1928 hdmi_pin { 1929 hdmi_cec: hdmi-cec { 1930 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1931 }; 1932 1933 hdmi_hpd: hdmi-hpd { 1934 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1935 }; 1936 }; 1937 1938 cif-0 { 1939 dvp_d2d9_m0:dvp-d2d9-m0 { 1940 rockchip,pins = 1941 /* cif_d0 */ 1942 <3 RK_PA4 2 &pcfg_pull_none>, 1943 /* cif_d1 */ 1944 <3 RK_PA5 2 &pcfg_pull_none>, 1945 /* cif_d2 */ 1946 <3 RK_PA6 2 &pcfg_pull_none>, 1947 /* cif_d3 */ 1948 <3 RK_PA7 2 &pcfg_pull_none>, 1949 /* cif_d4 */ 1950 <3 RK_PB0 2 &pcfg_pull_none>, 1951 /* cif_d5m0 */ 1952 <3 RK_PB1 2 &pcfg_pull_none>, 1953 /* cif_d6m0 */ 1954 <3 RK_PB2 2 &pcfg_pull_none>, 1955 /* cif_d7m0 */ 1956 <3 RK_PB3 2 &pcfg_pull_none>, 1957 /* cif_href */ 1958 <3 RK_PA1 2 &pcfg_pull_none>, 1959 /* cif_vsync */ 1960 <3 RK_PA0 2 &pcfg_pull_none>, 1961 /* cif_clkoutm0 */ 1962 <3 RK_PA3 2 &pcfg_pull_none>, 1963 /* cif_clkin */ 1964 <3 RK_PA2 2 &pcfg_pull_none>; 1965 }; 1966 }; 1967 1968 cif-1 { 1969 dvp_d2d9_m1:dvp-d2d9-m1 { 1970 rockchip,pins = 1971 /* cif_d0 */ 1972 <3 RK_PA4 2 &pcfg_pull_none>, 1973 /* cif_d1 */ 1974 <3 RK_PA5 2 &pcfg_pull_none>, 1975 /* cif_d2 */ 1976 <3 RK_PA6 2 &pcfg_pull_none>, 1977 /* cif_d3 */ 1978 <3 RK_PA7 2 &pcfg_pull_none>, 1979 /* cif_d4 */ 1980 <3 RK_PB0 2 &pcfg_pull_none>, 1981 /* cif_d5m1 */ 1982 <2 RK_PC0 4 &pcfg_pull_none>, 1983 /* cif_d6m1 */ 1984 <2 RK_PC1 4 &pcfg_pull_none>, 1985 /* cif_d7m1 */ 1986 <2 RK_PC2 4 &pcfg_pull_none>, 1987 /* cif_href */ 1988 <3 RK_PA1 2 &pcfg_pull_none>, 1989 /* cif_vsync */ 1990 <3 RK_PA0 2 &pcfg_pull_none>, 1991 /* cif_clkoutm1 */ 1992 <2 RK_PB7 4 &pcfg_pull_none>, 1993 /* cif_clkin */ 1994 <3 RK_PA2 2 &pcfg_pull_none>; 1995 }; 1996 }; 1997 }; 1998}; 1999