1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos850 SoC device tree source 4 * 5 * Copyright (C) 2018 Samsung Electronics Co., Ltd. 6 * Copyright (C) 2021 Linaro Ltd. 7 * 8 * Samsung Exynos850 SoC device nodes are listed in this file. 9 * Exynos850 based board files can include this file and provide 10 * values for board specific bindings. 11 */ 12 13#include <dt-bindings/clock/exynos850.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/samsung,exynos-usi.h> 16 17/ { 18 /* Also known under engineering name Exynos3830 */ 19 compatible = "samsung,exynos850"; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_cmgp; 28 pinctrl2 = &pinctrl_aud; 29 pinctrl3 = &pinctrl_hsi; 30 pinctrl4 = &pinctrl_core; 31 pinctrl5 = &pinctrl_peri; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a55-pmu"; 36 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 45 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 46 }; 47 48 /* Main system clock (XTCXO); external, must be 26 MHz */ 49 oscclk: clock-oscclk { 50 compatible = "fixed-clock"; 51 clock-output-names = "oscclk"; 52 #clock-cells = <0>; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu0>; 63 }; 64 core1 { 65 cpu = <&cpu1>; 66 }; 67 core2 { 68 cpu = <&cpu2>; 69 }; 70 core3 { 71 cpu = <&cpu3>; 72 }; 73 }; 74 75 cluster1 { 76 core0 { 77 cpu = <&cpu4>; 78 }; 79 core1 { 80 cpu = <&cpu5>; 81 }; 82 core2 { 83 cpu = <&cpu6>; 84 }; 85 core3 { 86 cpu = <&cpu7>; 87 }; 88 }; 89 }; 90 91 cpu0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>; 97 clock-names = "cluster0_clk"; 98 }; 99 cpu1: cpu@1 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x1>; 103 enable-method = "psci"; 104 }; 105 cpu2: cpu@2 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a55"; 108 reg = <0x2>; 109 enable-method = "psci"; 110 }; 111 cpu3: cpu@3 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a55"; 114 reg = <0x3>; 115 enable-method = "psci"; 116 }; 117 cpu4: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a55"; 120 reg = <0x100>; 121 enable-method = "psci"; 122 clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>; 123 clock-names = "cluster1_clk"; 124 }; 125 cpu5: cpu@101 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a55"; 128 reg = <0x101>; 129 enable-method = "psci"; 130 }; 131 cpu6: cpu@102 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a55"; 134 reg = <0x102>; 135 enable-method = "psci"; 136 }; 137 cpu7: cpu@103 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a55"; 140 reg = <0x103>; 141 enable-method = "psci"; 142 }; 143 }; 144 145 psci { 146 compatible = "arm,psci-1.0"; 147 method = "smc"; 148 }; 149 150 timer { 151 compatible = "arm,armv8-timer"; 152 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 153 interrupts = 154 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 158 }; 159 160 soc: soc@0 { 161 compatible = "simple-bus"; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges = <0x0 0x0 0x0 0x20000000>; 165 166 chipid@10000000 { 167 compatible = "samsung,exynos850-chipid"; 168 reg = <0x10000000 0x100>; 169 }; 170 171 timer@10040000 { 172 compatible = "samsung,exynos850-mct", 173 "samsung,exynos4210-mct"; 174 reg = <0x10040000 0x800>; 175 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; 188 clock-names = "fin_pll", "mct"; 189 }; 190 191 pdma0: dma-controller@120c0000 { 192 compatible = "arm,pl330", "arm,primecell"; 193 reg = <0x120c0000 0x1000>; 194 clocks = <&cmu_core CLK_GOUT_PDMA_CORE_ACLK>; 195 clock-names = "apb_pclk"; 196 #dma-cells = <1>; 197 interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>; 198 arm,pl330-broken-no-flushp; 199 }; 200 201 gic: interrupt-controller@12a01000 { 202 compatible = "arm,gic-400"; 203 #interrupt-cells = <3>; 204 #address-cells = <0>; 205 reg = <0x12a01000 0x1000>, 206 <0x12a02000 0x2000>, 207 <0x12a04000 0x2000>, 208 <0x12a06000 0x2000>; 209 interrupt-controller; 210 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 211 IRQ_TYPE_LEVEL_HIGH)>; 212 }; 213 214 pmu_system_controller: system-controller@11860000 { 215 compatible = "samsung,exynos850-pmu", "syscon"; 216 reg = <0x11860000 0x10000>; 217 218 poweroff: syscon-poweroff { 219 compatible = "syscon-poweroff"; 220 offset = <0x30c>; /* PS_HOLD_CONTROL */ 221 mask = <0x00000100>; 222 value = <0x0>; 223 }; 224 225 reboot: syscon-reboot { 226 compatible = "syscon-reboot"; 227 regmap = <&pmu_system_controller>; 228 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 229 mask = <0x2>; /* SWRESET_SYSTEM */ 230 value = <0x2>; /* reset value */ 231 }; 232 }; 233 234 watchdog_cl0: watchdog@10050000 { 235 compatible = "samsung,exynos850-wdt"; 236 reg = <0x10050000 0x100>; 237 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; 239 clock-names = "watchdog", "watchdog_src"; 240 samsung,syscon-phandle = <&pmu_system_controller>; 241 samsung,cluster-index = <0>; 242 status = "disabled"; 243 }; 244 245 watchdog_cl1: watchdog@10060000 { 246 compatible = "samsung,exynos850-wdt"; 247 reg = <0x10060000 0x100>; 248 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; 250 clock-names = "watchdog", "watchdog_src"; 251 samsung,syscon-phandle = <&pmu_system_controller>; 252 samsung,cluster-index = <1>; 253 status = "disabled"; 254 }; 255 256 cmu_peri: clock-controller@10030000 { 257 compatible = "samsung,exynos850-cmu-peri"; 258 reg = <0x10030000 0x8000>; 259 #clock-cells = <1>; 260 261 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, 262 <&cmu_top CLK_DOUT_PERI_UART>, 263 <&cmu_top CLK_DOUT_PERI_IP>; 264 clock-names = "oscclk", "dout_peri_bus", 265 "dout_peri_uart", "dout_peri_ip"; 266 }; 267 268 cmu_cpucl1: clock-controller@10800000 { 269 compatible = "samsung,exynos850-cmu-cpucl1"; 270 reg = <0x10800000 0x8000>; 271 #clock-cells = <1>; 272 273 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>, 274 <&cmu_top CLK_DOUT_CPUCL1_DBG>; 275 clock-names = "oscclk", "dout_cpucl1_switch", 276 "dout_cpucl1_dbg"; 277 }; 278 279 cmu_cpucl0: clock-controller@10900000 { 280 compatible = "samsung,exynos850-cmu-cpucl0"; 281 reg = <0x10900000 0x8000>; 282 #clock-cells = <1>; 283 284 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>, 285 <&cmu_top CLK_DOUT_CPUCL0_DBG>; 286 clock-names = "oscclk", "dout_cpucl0_switch", 287 "dout_cpucl0_dbg"; 288 }; 289 290 cmu_g3d: clock-controller@11400000 { 291 compatible = "samsung,exynos850-cmu-g3d"; 292 reg = <0x11400000 0x8000>; 293 #clock-cells = <1>; 294 295 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; 296 clock-names = "oscclk", "dout_g3d_switch"; 297 }; 298 299 cmu_apm: clock-controller@11800000 { 300 compatible = "samsung,exynos850-cmu-apm"; 301 reg = <0x11800000 0x8000>; 302 #clock-cells = <1>; 303 304 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; 305 clock-names = "oscclk", "dout_clkcmu_apm_bus"; 306 }; 307 308 cmu_cmgp: clock-controller@11c00000 { 309 compatible = "samsung,exynos850-cmu-cmgp"; 310 reg = <0x11c00000 0x8000>; 311 #clock-cells = <1>; 312 313 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; 314 clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; 315 }; 316 317 cmu_core: clock-controller@12000000 { 318 compatible = "samsung,exynos850-cmu-core"; 319 reg = <0x12000000 0x8000>; 320 #clock-cells = <1>; 321 322 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, 323 <&cmu_top CLK_DOUT_CORE_CCI>, 324 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, 325 <&cmu_top CLK_DOUT_CORE_SSS>; 326 clock-names = "oscclk", "dout_core_bus", 327 "dout_core_cci", "dout_core_mmc_embd", 328 "dout_core_sss"; 329 }; 330 331 cmu_top: clock-controller@120e0000 { 332 compatible = "samsung,exynos850-cmu-top"; 333 reg = <0x120e0000 0x8000>; 334 #clock-cells = <1>; 335 336 clocks = <&oscclk>; 337 clock-names = "oscclk"; 338 }; 339 340 cmu_mfcmscl: clock-controller@12c00000 { 341 compatible = "samsung,exynos850-cmu-mfcmscl"; 342 reg = <0x12c00000 0x8000>; 343 #clock-cells = <1>; 344 345 clocks = <&oscclk>, 346 <&cmu_top CLK_DOUT_MFCMSCL_MFC>, 347 <&cmu_top CLK_DOUT_MFCMSCL_M2M>, 348 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, 349 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; 350 clock-names = "oscclk", "dout_mfcmscl_mfc", 351 "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", 352 "dout_mfcmscl_jpeg"; 353 }; 354 355 cmu_dpu: clock-controller@13000000 { 356 compatible = "samsung,exynos850-cmu-dpu"; 357 reg = <0x13000000 0x8000>; 358 #clock-cells = <1>; 359 360 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; 361 clock-names = "oscclk", "dout_dpu"; 362 }; 363 364 cmu_hsi: clock-controller@13400000 { 365 compatible = "samsung,exynos850-cmu-hsi"; 366 reg = <0x13400000 0x8000>; 367 #clock-cells = <1>; 368 369 clocks = <&oscclk>, 370 <&cmu_top CLK_DOUT_HSI_BUS>, 371 <&cmu_top CLK_DOUT_HSI_MMC_CARD>, 372 <&cmu_top CLK_DOUT_HSI_USB20DRD>; 373 clock-names = "oscclk", "dout_hsi_bus", 374 "dout_hsi_mmc_card", "dout_hsi_usb20drd"; 375 }; 376 377 cmu_is: clock-controller@14500000 { 378 compatible = "samsung,exynos850-cmu-is"; 379 reg = <0x14500000 0x8000>; 380 #clock-cells = <1>; 381 382 clocks = <&oscclk>, 383 <&cmu_top CLK_DOUT_IS_BUS>, 384 <&cmu_top CLK_DOUT_IS_ITP>, 385 <&cmu_top CLK_DOUT_IS_VRA>, 386 <&cmu_top CLK_DOUT_IS_GDC>; 387 clock-names = "oscclk", "dout_is_bus", "dout_is_itp", 388 "dout_is_vra", "dout_is_gdc"; 389 }; 390 391 cmu_aud: clock-controller@14a00000 { 392 compatible = "samsung,exynos850-cmu-aud"; 393 reg = <0x14a00000 0x8000>; 394 #clock-cells = <1>; 395 396 clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; 397 clock-names = "oscclk", "dout_aud"; 398 }; 399 400 pinctrl_alive: pinctrl@11850000 { 401 compatible = "samsung,exynos850-pinctrl"; 402 reg = <0x11850000 0x1000>; 403 404 wakeup-interrupt-controller { 405 compatible = "samsung,exynos850-wakeup-eint", 406 "samsung,exynos7-wakeup-eint"; 407 }; 408 }; 409 410 pinctrl_cmgp: pinctrl@11c30000 { 411 compatible = "samsung,exynos850-pinctrl"; 412 reg = <0x11c30000 0x1000>; 413 414 wakeup-interrupt-controller { 415 compatible = "samsung,exynos850-wakeup-eint", 416 "samsung,exynos7-wakeup-eint"; 417 }; 418 }; 419 420 pinctrl_core: pinctrl@12070000 { 421 compatible = "samsung,exynos850-pinctrl"; 422 reg = <0x12070000 0x1000>; 423 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 424 }; 425 426 trng: rng@12081400 { 427 compatible = "samsung,exynos850-trng"; 428 reg = <0x12081400 0x100>; 429 clocks = <&cmu_core CLK_GOUT_SSS_ACLK>, 430 <&cmu_core CLK_GOUT_SSS_PCLK>; 431 clock-names = "secss", "pclk"; 432 }; 433 434 pinctrl_hsi: pinctrl@13430000 { 435 compatible = "samsung,exynos850-pinctrl"; 436 reg = <0x13430000 0x1000>; 437 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 438 }; 439 440 pinctrl_peri: pinctrl@139b0000 { 441 compatible = "samsung,exynos850-pinctrl"; 442 reg = <0x139b0000 0x1000>; 443 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 444 }; 445 446 pinctrl_aud: pinctrl@14a60000 { 447 compatible = "samsung,exynos850-pinctrl"; 448 reg = <0x14a60000 0x1000>; 449 }; 450 451 rtc: rtc@11a30000 { 452 compatible = "samsung,exynos850-rtc", "samsung,s3c6410-rtc"; 453 reg = <0x11a30000 0x100>; 454 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; 457 clock-names = "rtc"; 458 status = "disabled"; 459 }; 460 461 mmc_0: mmc@12100000 { 462 compatible = "samsung,exynos850-dw-mshc-smu", 463 "samsung,exynos7-dw-mshc-smu"; 464 reg = <0x12100000 0x2000>; 465 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, 469 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; 470 clock-names = "biu", "ciu"; 471 fifo-depth = <0x40>; 472 status = "disabled"; 473 }; 474 475 i2c_0: i2c@13830000 { 476 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 477 reg = <0x13830000 0x100>; 478 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&i2c0_pins>; 483 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 484 clock-names = "i2c"; 485 status = "disabled"; 486 }; 487 488 i2c_1: i2c@13840000 { 489 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 490 reg = <0x13840000 0x100>; 491 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&i2c1_pins>; 496 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 497 clock-names = "i2c"; 498 status = "disabled"; 499 }; 500 501 i2c_2: i2c@13850000 { 502 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 503 reg = <0x13850000 0x100>; 504 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&i2c2_pins>; 509 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 510 clock-names = "i2c"; 511 status = "disabled"; 512 }; 513 514 i2c_3: i2c@13860000 { 515 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 516 reg = <0x13860000 0x100>; 517 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&i2c3_pins>; 522 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 523 clock-names = "i2c"; 524 status = "disabled"; 525 }; 526 527 i2c_4: i2c@13870000 { 528 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 529 reg = <0x13870000 0x100>; 530 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&i2c4_pins>; 535 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 536 clock-names = "i2c"; 537 status = "disabled"; 538 }; 539 540 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ 541 i2c_5: i2c@13880000 { 542 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 543 reg = <0x13880000 0x100>; 544 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c5_pins>; 549 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 550 clock-names = "i2c"; 551 status = "disabled"; 552 }; 553 554 /* I2C_6 (also called MOTOR_I2C in TRM) */ 555 i2c_6: i2c@13890000 { 556 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 557 reg = <0x13890000 0x100>; 558 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&i2c6_pins>; 563 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 564 clock-names = "i2c"; 565 status = "disabled"; 566 }; 567 568 sysmmu_mfcmscl: sysmmu@12c50000 { 569 compatible = "samsung,exynos-sysmmu"; 570 reg = <0x12c50000 0x9000>; 571 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 572 clock-names = "sysmmu"; 573 clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; 574 #iommu-cells = <0>; 575 }; 576 577 sysmmu_dpu: sysmmu@130c0000 { 578 compatible = "samsung,exynos-sysmmu"; 579 reg = <0x130c0000 0x9000>; 580 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 581 clock-names = "sysmmu"; 582 clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; 583 #iommu-cells = <0>; 584 }; 585 586 sysmmu_is0: sysmmu@14550000 { 587 compatible = "samsung,exynos-sysmmu"; 588 reg = <0x14550000 0x9000>; 589 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 590 clock-names = "sysmmu"; 591 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; 592 #iommu-cells = <0>; 593 }; 594 595 sysmmu_is1: sysmmu@14570000 { 596 compatible = "samsung,exynos-sysmmu"; 597 reg = <0x14570000 0x9000>; 598 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 599 clock-names = "sysmmu"; 600 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; 601 #iommu-cells = <0>; 602 }; 603 604 sysmmu_aud: sysmmu@14850000 { 605 compatible = "samsung,exynos-sysmmu"; 606 reg = <0x14850000 0x9000>; 607 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 608 clock-names = "sysmmu"; 609 clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; 610 #iommu-cells = <0>; 611 }; 612 613 sysreg_peri: syscon@10020000 { 614 compatible = "samsung,exynos850-peri-sysreg", 615 "samsung,exynos850-sysreg", "syscon"; 616 reg = <0x10020000 0x10000>; 617 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; 618 }; 619 620 sysreg_cmgp: syscon@11c20000 { 621 compatible = "samsung,exynos850-cmgp-sysreg", 622 "samsung,exynos850-sysreg", "syscon"; 623 reg = <0x11c20000 0x10000>; 624 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; 625 }; 626 627 usbdrd: usb@13600000 { 628 compatible = "samsung,exynos850-dwusb3"; 629 ranges = <0x0 0x13600000 0x10000>; 630 clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>, 631 <&cmu_hsi CLK_GOUT_USB_REF_CLK>; 632 clock-names = "bus_early", "ref"; 633 #address-cells = <1>; 634 #size-cells = <1>; 635 status = "disabled"; 636 637 usbdrd_dwc3: usb@0 { 638 compatible = "snps,dwc3"; 639 reg = <0x0 0x10000>; 640 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 641 phys = <&usbdrd_phy 0>; 642 phy-names = "usb2-phy"; 643 }; 644 }; 645 646 usbdrd_phy: phy@135d0000 { 647 compatible = "samsung,exynos850-usbdrd-phy"; 648 reg = <0x135d0000 0x100>; 649 clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>, 650 <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>; 651 clock-names = "phy", "ref"; 652 samsung,pmu-syscon = <&pmu_system_controller>; 653 #phy-cells = <1>; 654 status = "disabled"; 655 }; 656 657 usi_uart: usi@138200c0 { 658 compatible = "samsung,exynos850-usi"; 659 reg = <0x138200c0 0x20>; 660 samsung,sysreg = <&sysreg_peri 0x1010>; 661 samsung,mode = <USI_MODE_UART>; 662 #address-cells = <1>; 663 #size-cells = <1>; 664 ranges; 665 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 666 <&cmu_peri CLK_GOUT_UART_IPCLK>; 667 clock-names = "pclk", "ipclk"; 668 status = "disabled"; 669 670 serial_0: serial@13820000 { 671 compatible = "samsung,exynos850-uart"; 672 reg = <0x13820000 0xc0>; 673 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&uart0_pins>; 676 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 677 <&cmu_peri CLK_GOUT_UART_IPCLK>; 678 clock-names = "uart", "clk_uart_baud0"; 679 status = "disabled"; 680 }; 681 }; 682 683 usi_hsi2c_0: usi@138a00c0 { 684 compatible = "samsung,exynos850-usi"; 685 reg = <0x138a00c0 0x20>; 686 samsung,sysreg = <&sysreg_peri 0x1020>; 687 samsung,mode = <USI_MODE_I2C>; 688 #address-cells = <1>; 689 #size-cells = <1>; 690 ranges; 691 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, 692 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; 693 clock-names = "pclk", "ipclk"; 694 status = "disabled"; 695 696 hsi2c_0: i2c@138a0000 { 697 compatible = "samsung,exynos850-hsi2c", 698 "samsung,exynosautov9-hsi2c"; 699 reg = <0x138a0000 0xc0>; 700 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 701 #address-cells = <1>; 702 #size-cells = <0>; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&hsi2c0_pins>; 705 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, 706 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; 707 clock-names = "hsi2c", "hsi2c_pclk"; 708 status = "disabled"; 709 }; 710 }; 711 712 usi_hsi2c_1: usi@138b00c0 { 713 compatible = "samsung,exynos850-usi"; 714 reg = <0x138b00c0 0x20>; 715 samsung,sysreg = <&sysreg_peri 0x1030>; 716 samsung,mode = <USI_MODE_I2C>; 717 #address-cells = <1>; 718 #size-cells = <1>; 719 ranges; 720 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, 721 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; 722 clock-names = "pclk", "ipclk"; 723 status = "disabled"; 724 725 hsi2c_1: i2c@138b0000 { 726 compatible = "samsung,exynos850-hsi2c", 727 "samsung,exynosautov9-hsi2c"; 728 reg = <0x138b0000 0xc0>; 729 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 pinctrl-names = "default"; 733 pinctrl-0 = <&hsi2c1_pins>; 734 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, 735 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; 736 clock-names = "hsi2c", "hsi2c_pclk"; 737 status = "disabled"; 738 }; 739 }; 740 741 usi_hsi2c_2: usi@138c00c0 { 742 compatible = "samsung,exynos850-usi"; 743 reg = <0x138c00c0 0x20>; 744 samsung,sysreg = <&sysreg_peri 0x1040>; 745 samsung,mode = <USI_MODE_I2C>; 746 #address-cells = <1>; 747 #size-cells = <1>; 748 ranges; 749 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, 750 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; 751 clock-names = "pclk", "ipclk"; 752 status = "disabled"; 753 754 hsi2c_2: i2c@138c0000 { 755 compatible = "samsung,exynos850-hsi2c", 756 "samsung,exynosautov9-hsi2c"; 757 reg = <0x138c0000 0xc0>; 758 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 pinctrl-names = "default"; 762 pinctrl-0 = <&hsi2c2_pins>; 763 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, 764 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; 765 clock-names = "hsi2c", "hsi2c_pclk"; 766 status = "disabled"; 767 }; 768 }; 769 770 usi_spi_0: usi@139400c0 { 771 compatible = "samsung,exynos850-usi"; 772 reg = <0x139400c0 0x20>; 773 samsung,sysreg = <&sysreg_peri 0x1050>; 774 samsung,mode = <USI_MODE_SPI>; 775 #address-cells = <1>; 776 #size-cells = <1>; 777 ranges; 778 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 779 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 780 clock-names = "pclk", "ipclk"; 781 status = "disabled"; 782 783 spi_0: spi@13940000 { 784 compatible = "samsung,exynos850-spi"; 785 reg = <0x13940000 0x30>; 786 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 787 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 788 clock-names = "spi", "spi_busclk0"; 789 dmas = <&pdma0 5>, <&pdma0 4>; 790 dma-names = "tx", "rx"; 791 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 792 pinctrl-0 = <&spi0_pins>; 793 pinctrl-names = "default"; 794 num-cs = <1>; 795 samsung,spi-src-clk = <0>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 status = "disabled"; 799 }; 800 }; 801 802 usi_cmgp0: usi@11d000c0 { 803 compatible = "samsung,exynos850-usi"; 804 reg = <0x11d000c0 0x20>; 805 samsung,sysreg = <&sysreg_cmgp 0x2000>; 806 samsung,mode = <USI_MODE_I2C>; 807 #address-cells = <1>; 808 #size-cells = <1>; 809 ranges; 810 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 811 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 812 clock-names = "pclk", "ipclk"; 813 status = "disabled"; 814 815 hsi2c_3: i2c@11d00000 { 816 compatible = "samsung,exynos850-hsi2c", 817 "samsung,exynosautov9-hsi2c"; 818 reg = <0x11d00000 0xc0>; 819 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&hsi2c3_pins>; 824 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, 825 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; 826 clock-names = "hsi2c", "hsi2c_pclk"; 827 status = "disabled"; 828 }; 829 830 serial_1: serial@11d00000 { 831 compatible = "samsung,exynos850-uart"; 832 reg = <0x11d00000 0xc0>; 833 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&uart1_single_pins>; 836 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 837 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 838 clock-names = "uart", "clk_uart_baud0"; 839 status = "disabled"; 840 }; 841 842 spi_1: spi@11d00000 { 843 compatible = "samsung,exynos850-spi"; 844 reg = <0x11d00000 0x30>; 845 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 846 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 847 clock-names = "spi", "spi_busclk0"; 848 dmas = <&pdma0 12>, <&pdma0 13>; 849 dma-names = "tx", "rx"; 850 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 851 pinctrl-0 = <&spi1_pins>; 852 pinctrl-names = "default"; 853 num-cs = <1>; 854 samsung,spi-src-clk = <0>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 status = "disabled"; 858 }; 859 }; 860 861 usi_cmgp1: usi@11d200c0 { 862 compatible = "samsung,exynos850-usi"; 863 reg = <0x11d200c0 0x20>; 864 samsung,sysreg = <&sysreg_cmgp 0x2010>; 865 samsung,mode = <USI_MODE_I2C>; 866 #address-cells = <1>; 867 #size-cells = <1>; 868 ranges; 869 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 870 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 871 clock-names = "pclk", "ipclk"; 872 status = "disabled"; 873 874 hsi2c_4: i2c@11d20000 { 875 compatible = "samsung,exynos850-hsi2c", 876 "samsung,exynosautov9-hsi2c"; 877 reg = <0x11d20000 0xc0>; 878 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&hsi2c4_pins>; 883 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, 884 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; 885 clock-names = "hsi2c", "hsi2c_pclk"; 886 status = "disabled"; 887 }; 888 889 serial_2: serial@11d20000 { 890 compatible = "samsung,exynos850-uart"; 891 reg = <0x11d20000 0xc0>; 892 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&uart2_single_pins>; 895 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 896 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 897 clock-names = "uart", "clk_uart_baud0"; 898 status = "disabled"; 899 }; 900 901 spi_2: spi@11d20000 { 902 compatible = "samsung,exynos850-spi"; 903 reg = <0x11d20000 0x30>; 904 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 905 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 906 clock-names = "spi", "spi_busclk0"; 907 dmas = <&pdma0 14>, <&pdma0 15>; 908 dma-names = "tx", "rx"; 909 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 910 pinctrl-0 = <&spi2_pins>; 911 pinctrl-names = "default"; 912 num-cs = <1>; 913 samsung,spi-src-clk = <0>; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 }; 919 }; 920}; 921 922#include "exynos850-pinctrl.dtsi" 923