1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Generic Pin Controller with a Single Register for One or More Pins 8 9maintainers: 10 - Tony Lindgren <tony@atomide.com> 11 12description: 13 Some pin controller devices use a single register for one or more pins. The 14 range of pin control registers can vary from one to many for each controller 15 instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this 16 kind of pin controller instances. 17 18properties: 19 compatible: 20 oneOf: 21 - enum: 22 - pinctrl-single 23 - pinconf-single 24 - items: 25 - enum: 26 - ti,am437-padconf 27 - ti,am654-padconf 28 - ti,dra7-padconf 29 - ti,omap2420-padconf 30 - ti,omap2430-padconf 31 - ti,omap3-padconf 32 - ti,omap4-padconf 33 - ti,omap5-padconf 34 - ti,j7200-padconf 35 - const: pinctrl-single 36 - items: 37 - enum: 38 - marvell,pxa1908-padconf 39 - const: pinconf-single 40 41 reg: 42 maxItems: 1 43 44 interrupt-controller: true 45 46 '#interrupt-cells': 47 const: 1 48 49 '#address-cells': 50 const: 1 51 52 '#size-cells': 53 const: 0 54 55 '#pinctrl-cells': 56 description: 57 Number of cells. Usually 2, consisting of register offset, pin configuration 58 value, and pinmux mode. Some controllers may use 1 for just offset and value. 59 enum: [ 1, 2 ] 60 61 pinctrl-single,bit-per-mux: 62 description: Optional flag to indicate register controls more than one pin 63 type: boolean 64 65 pinctrl-single,function-mask: 66 description: Mask of the allowed register bits 67 $ref: /schemas/types.yaml#/definitions/uint32 68 69 pinctrl-single,function-off: 70 description: Optional function off mode for disabled state 71 $ref: /schemas/types.yaml#/definitions/uint32 72 73 pinctrl-single,register-width: 74 description: Width of pin specific bits in the register 75 $ref: /schemas/types.yaml#/definitions/uint32 76 enum: [ 8, 16, 32 ] 77 78 pinctrl-single,gpio-range: 79 description: Optional list of pin base, nr pins & gpio function 80 $ref: /schemas/types.yaml#/definitions/phandle-array 81 items: 82 items: 83 - description: phandle of a gpio-range node 84 - description: pin base 85 - description: number of pins 86 - description: gpio function 87 88 '#gpio-range-cells': 89 description: No longer needed, may exist in older files for gpio-ranges 90 deprecated: true 91 const: 3 92 93 gpio-range: 94 description: Optional node for gpio range cells 95 type: object 96 additionalProperties: false 97 properties: 98 '#pinctrl-single,gpio-range-cells': 99 description: Number of gpio range cells 100 const: 3 101 $ref: /schemas/types.yaml#/definitions/uint32 102 103patternProperties: 104 '-pins(-[0-9]+)?$|-pin$': 105 description: 106 Pin group node name using naming ending in -pins followed by an optional 107 instance number 108 type: object 109 additionalProperties: false 110 111 properties: 112 pinctrl-single,pins: 113 description: 114 Array of pins as described in pinmux-node.yaml for pinctrl-pin-array 115 $ref: /schemas/types.yaml#/definitions/uint32-array 116 117 pinctrl-single,bits: 118 description: Register bit configuration for pinctrl-single,bit-per-mux 119 $ref: /schemas/types.yaml#/definitions/uint32-array 120 items: 121 - description: register offset 122 - description: value 123 - description: pin bitmask in the register 124 125 pinctrl-single,bias-pullup: 126 description: Optional bias pull up configuration 127 $ref: /schemas/types.yaml#/definitions/uint32-array 128 items: 129 - description: input 130 - description: enabled pull up bits 131 - description: disabled pull up bits 132 - description: bias pull up mask 133 134 pinctrl-single,bias-pulldown: 135 description: Optional bias pull down configuration 136 $ref: /schemas/types.yaml#/definitions/uint32-array 137 items: 138 - description: input 139 - description: enabled pull down bits 140 - description: disabled pull down bits 141 - description: bias pull down mask 142 143 pinctrl-single,drive-strength: 144 description: Optional drive strength configuration 145 $ref: /schemas/types.yaml#/definitions/uint32-array 146 items: 147 - description: drive strength current 148 - description: drive strength mask 149 150 pinctrl-single,input-schmitt: 151 description: Optional schmitt strength configuration 152 $ref: /schemas/types.yaml#/definitions/uint32-array 153 items: 154 - description: schmitt strength current 155 - description: schmitt strength mask 156 157 pinctrl-single,input-schmitt-enable: 158 description: Optional input schmitt configuration 159 $ref: /schemas/types.yaml#/definitions/uint32-array 160 items: 161 - description: input 162 - description: enable bits 163 - description: disable bits 164 - description: input schmitt mask 165 166 pinctrl-single,low-power-mode: 167 description: Optional low power mode configuration 168 $ref: /schemas/types.yaml#/definitions/uint32-array 169 items: 170 - description: low power mode value 171 - description: low power mode mask 172 173 pinctrl-single,slew-rate: 174 description: Optional slew rate configuration 175 $ref: /schemas/types.yaml#/definitions/uint32-array 176 items: 177 - description: slew rate 178 - description: slew rate mask 179 180allOf: 181 - $ref: pinctrl.yaml# 182 183required: 184 - compatible 185 - reg 186 - pinctrl-single,register-width 187 188additionalProperties: false 189 190examples: 191 - | 192 soc { 193 #address-cells = <1>; 194 #size-cells = <1>; 195 196 pinmux@4a100040 { 197 compatible = "pinctrl-single"; 198 reg = <0x4a100040 0x0196>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 #pinctrl-cells = <2>; 202 #interrupt-cells = <1>; 203 interrupt-controller; 204 pinctrl-single,register-width = <16>; 205 pinctrl-single,function-mask = <0xffff>; 206 pinctrl-single,gpio-range = <&range 0 3 0>; 207 range: gpio-range { 208 #pinctrl-single,gpio-range-cells = <3>; 209 }; 210 211 uart2-pins { 212 pinctrl-single,pins = 213 <0xd8 0x118>, 214 <0xda 0>, 215 <0xdc 0x118>, 216 <0xde 0>; 217 }; 218 }; 219 }; 220