1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dpll/dpll-pin.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: DPLL Pin 8 9maintainers: 10 - Ivan Vecera <ivecera@redhat.com> 11 12description: | 13 The DPLL pin is either a physical input or output pin that is provided 14 by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by 15 its physical order number that is stored in reg property and can have 16 an additional set of properties like supported (allowed) frequencies, 17 label, type and may support embedded sync. 18 19 Note that the pin in this context has nothing to do with pinctrl. 20 21properties: 22 reg: 23 description: Hardware index of the DPLL pin. 24 maxItems: 1 25 26 connection-type: 27 description: Connection type of the pin 28 $ref: /schemas/types.yaml#/definitions/string 29 enum: [ext, gnss, int, mux, synce] 30 31 esync-control: 32 description: Indicates whether the pin supports embedded sync functionality. 33 type: boolean 34 35 label: 36 description: String exposed as the pin board label 37 $ref: /schemas/types.yaml#/definitions/string 38 39 supported-frequencies-hz: 40 description: List of supported frequencies for this pin, expressed in Hz. 41 42required: 43 - reg 44 45additionalProperties: false 46