1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation.
3 */
4
5 #include "main.h"
6 #include "reg.h"
7 #include "bf.h"
8 #include "debug.h"
9
rtw_bf_disassoc(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)10 void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
11 struct ieee80211_bss_conf *bss_conf)
12 {
13 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
14 struct rtw_bfee *bfee = &rtwvif->bfee;
15 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
16
17 if (bfee->role == RTW_BFEE_NONE)
18 return;
19
20 if (bfee->role == RTW_BFEE_MU)
21 bfinfo->bfer_mu_cnt--;
22 else if (bfee->role == RTW_BFEE_SU)
23 bfinfo->bfer_su_cnt--;
24
25 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false);
26
27 bfee->role = RTW_BFEE_NONE;
28 }
29
rtw_bf_assoc(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf)30 void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
31 struct ieee80211_bss_conf *bss_conf)
32 {
33 const struct rtw_chip_info *chip = rtwdev->chip;
34 struct ieee80211_hw *hw = rtwdev->hw;
35 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
36 struct rtw_bfee *bfee = &rtwvif->bfee;
37 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
38 struct ieee80211_sta *sta;
39 struct ieee80211_sta_vht_cap *vht_cap;
40 struct ieee80211_sta_vht_cap *ic_vht_cap;
41 const u8 *bssid = bss_conf->bssid;
42 u32 sound_dim;
43 u8 i;
44
45 if (!(chip->band & RTW_BAND_5G))
46 return;
47
48 rcu_read_lock();
49
50 sta = ieee80211_find_sta(vif, bssid);
51 if (!sta) {
52 rcu_read_unlock();
53
54 rtw_warn(rtwdev, "failed to find station entry for bss %pM\n",
55 bssid);
56 return;
57 }
58
59 ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap;
60 vht_cap = &sta->deflink.vht_cap;
61
62 rcu_read_unlock();
63
64 if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) &&
65 (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) {
66 if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) {
67 rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n");
68 return;
69 }
70
71 ether_addr_copy(bfee->mac_addr, bssid);
72 bfee->role = RTW_BFEE_MU;
73 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
74 bfee->aid = vif->cfg.aid;
75 bfinfo->bfer_mu_cnt++;
76
77 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
78 } else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) &&
79 (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
80 if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) {
81 rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n");
82 return;
83 }
84
85 sound_dim = vht_cap->cap &
86 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK;
87 sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
88
89 ether_addr_copy(bfee->mac_addr, bssid);
90 bfee->role = RTW_BFEE_SU;
91 bfee->sound_dim = (u8)sound_dim;
92 bfee->g_id = 0;
93 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
94 bfinfo->bfer_su_cnt++;
95 for (i = 0; i < chip->bfer_su_max_num; i++) {
96 if (!test_bit(i, bfinfo->bfer_su_reg_maping)) {
97 set_bit(i, bfinfo->bfer_su_reg_maping);
98 bfee->su_reg_index = i;
99 break;
100 }
101 }
102
103 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
104 }
105 }
106
rtw_bf_init_bfer_entry_mu(struct rtw_dev * rtwdev,struct mu_bfer_init_para * param)107 void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
108 struct mu_bfer_init_para *param)
109 {
110 u16 mu_bf_ctl = 0;
111 u8 *addr = param->bfer_address;
112 int i;
113
114 for (i = 0; i < ETH_ALEN; i++)
115 rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]);
116 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
117 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
118
119 mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000;
120 mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12);
121 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl);
122 }
123
rtw_bf_cfg_sounding(struct rtw_dev * rtwdev,struct rtw_vif * vif,enum rtw_trx_desc_rate rate)124 void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
125 enum rtw_trx_desc_rate rate)
126 {
127 u8 csi_rsc = CSI_RSC_FOLLOW_RX_PACKET_BW;
128 u32 psf_ctl = 0;
129
130 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
131 csi_rsc = CSI_RSC_PRIMARY_20M_BW;
132
133 psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
134 BIT_WMAC_USE_NDPARATE |
135 (csi_rsc << 13);
136
137 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
138 RTW_SND_CTRL_SOUNDING);
139 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26);
140 rtwdev->hal.rxfltmap1 &= ~BIT_RXFLTMAP1_BF_REPORT_POLL;
141 rtw_write16(rtwdev, REG_RXFLTMAP1, rtwdev->hal.rxfltmap1);
142 rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL);
143
144 if (vif->net_type == RTW_NET_AP_MODE)
145 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12));
146 else
147 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12));
148 }
149
rtw_bf_cfg_mu_bfee(struct rtw_dev * rtwdev,struct cfg_mumimo_para * param)150 void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param)
151 {
152 u8 mu_tbl_sel;
153 u8 mu_valid;
154
155 mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) &
156 ~BIT_MASK_R_MU_TABLE_VALID;
157
158 rtw_write8(rtwdev, REG_MU_TX_CTL,
159 (mu_valid | BIT(0) | BIT(1)) & ~(BIT(7)));
160
161 mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8;
162
163 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel);
164 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
165 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
166 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
167 param->given_user_pos[1]);
168
169 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
170 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
171 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
172 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
173 param->given_user_pos[3]);
174 }
175
rtw_bf_del_bfer_entry_mu(struct rtw_dev * rtwdev)176 void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev)
177 {
178 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
179 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
180 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
181 rtw_write8(rtwdev, REG_MU_TX_CTL, 0);
182 }
183
rtw_bf_del_sounding(struct rtw_dev * rtwdev)184 void rtw_bf_del_sounding(struct rtw_dev *rtwdev)
185 {
186 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0);
187 }
188
rtw_bf_enable_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)189 void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
190 struct rtw_bfee *bfee)
191 {
192 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
193 u8 nr_index = bfee->sound_dim;
194 u8 grouping = 0, codebookinfo = 1, coefficientsize = 3;
195 u32 addr_bfer_info, addr_csi_rpt, csi_param;
196 u8 i;
197
198 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n");
199
200 switch (bfee->su_reg_index) {
201 case 1:
202 addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO;
203 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2;
204 break;
205 case 0:
206 default:
207 addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO;
208 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20;
209 break;
210 }
211
212 /* Sounding protocol control */
213 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
214 RTW_SND_CTRL_SOUNDING);
215
216 /* MAC address/Partial AID of Beamformer */
217 for (i = 0; i < ETH_ALEN; i++)
218 rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]);
219
220 csi_param = (u16)((coefficientsize << 10) |
221 (codebookinfo << 8) |
222 (grouping << 6) |
223 (nr_index << 3) |
224 nc_index);
225 rtw_write16(rtwdev, addr_csi_rpt, csi_param);
226
227 /* ndp rx standby timer */
228 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME);
229 }
230 EXPORT_SYMBOL(rtw_bf_enable_bfee_su);
231
232 /* nc index: 1 2T2R 0 1T1R
233 * nr index: 1 use Nsts 0 use reg setting
234 * codebookinfo: 1 802.11ac 3 802.11n
235 */
rtw_bf_enable_bfee_mu(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee)236 void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
237 struct rtw_bfee *bfee)
238 {
239 struct rtw_bf_info *bf_info = &rtwdev->bf_info;
240 struct mu_bfer_init_para param;
241 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
242 u8 nr_index = 1;
243 u8 grouping = 0, codebookinfo = 1, coefficientsize = 0;
244 u32 csi_param;
245
246 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n");
247
248 csi_param = (u16)((coefficientsize << 10) |
249 (codebookinfo << 8) |
250 (grouping << 6) |
251 (nr_index << 3) |
252 nc_index);
253
254 rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
255 nc_index, nr_index, grouping, codebookinfo,
256 coefficientsize);
257
258 param.paid = bfee->p_aid;
259 param.csi_para = csi_param;
260 param.my_aid = bfee->aid & 0xfff;
261 param.csi_length_sel = HAL_CSI_SEG_4K;
262 ether_addr_copy(param.bfer_address, bfee->mac_addr);
263
264 rtw_bf_init_bfer_entry_mu(rtwdev, ¶m);
265
266 bf_info->cur_csi_rpt_rate = DESC_RATE6M;
267 rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M);
268
269 /* accept action_no_ack */
270 rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK);
271
272 /* accept NDPA and BF report poll */
273 rtwdev->hal.rxfltmap1 |= BIT_RXFLTMAP1_BF;
274 rtw_write16(rtwdev, REG_RXFLTMAP1, rtwdev->hal.rxfltmap1);
275 }
276 EXPORT_SYMBOL(rtw_bf_enable_bfee_mu);
277
rtw_bf_remove_bfee_su(struct rtw_dev * rtwdev,struct rtw_bfee * bfee)278 void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev,
279 struct rtw_bfee *bfee)
280 {
281 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
282
283 rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n");
284 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
285 RTW_SND_CTRL_REMOVE);
286
287 switch (bfee->su_reg_index) {
288 case 0:
289 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
290 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
291 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0);
292 break;
293 case 1:
294 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0);
295 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
296 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0);
297 break;
298 }
299
300 clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping);
301 bfee->su_reg_index = 0xFF;
302 }
303 EXPORT_SYMBOL(rtw_bf_remove_bfee_su);
304
rtw_bf_remove_bfee_mu(struct rtw_dev * rtwdev,struct rtw_bfee * bfee)305 void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev,
306 struct rtw_bfee *bfee)
307 {
308 struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
309
310 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
311 RTW_SND_CTRL_REMOVE);
312
313 rtw_bf_del_bfer_entry_mu(rtwdev);
314
315 if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0)
316 rtw_bf_del_sounding(rtwdev);
317 }
318 EXPORT_SYMBOL(rtw_bf_remove_bfee_mu);
319
rtw_bf_set_gid_table(struct rtw_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf)320 void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
321 struct ieee80211_bss_conf *conf)
322 {
323 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
324 struct rtw_bfee *bfee = &rtwvif->bfee;
325 struct cfg_mumimo_para param;
326
327 if (bfee->role != RTW_BFEE_MU) {
328 rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n");
329 return;
330 }
331
332 param.grouping_bitmap = 0;
333 param.mu_tx_en = 0;
334 memset(param.sounding_sts, 0, 6);
335 memcpy(param.given_gid_tab, conf->mu_group.membership, 8);
336 memcpy(param.given_user_pos, conf->mu_group.position, 16);
337 rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
338 param.given_gid_tab[0], param.given_user_pos[0],
339 param.given_user_pos[1]);
340
341 rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
342 param.given_gid_tab[1], param.given_user_pos[2],
343 param.given_user_pos[3]);
344
345 rtw_bf_cfg_mu_bfee(rtwdev, ¶m);
346 }
347 EXPORT_SYMBOL(rtw_bf_set_gid_table);
348
rtw_bf_phy_init(struct rtw_dev * rtwdev)349 void rtw_bf_phy_init(struct rtw_dev *rtwdev)
350 {
351 u8 tmp8;
352 u32 tmp32;
353 u8 retry_limit = 0xA;
354 u8 ndpa_rate = 0x10;
355 u8 ack_policy = 3;
356
357 tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL);
358 /* Enable P1 aggr new packet according to P0 transfer time */
359 tmp32 |= BIT_MU_P1_WAIT_STATE_EN;
360 /* MU Retry Limit */
361 tmp32 &= ~BIT_MASK_R_MU_RL;
362 tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL;
363 /* Disable Tx MU-MIMO until sounding done */
364 tmp32 &= ~BIT_EN_MU_MIMO;
365 /* Clear validity of MU STAs */
366 tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID;
367 rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32);
368
369 /* MU-MIMO Option as default value */
370 tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY;
371 tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN;
372 rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8);
373
374 /* MU-MIMO Control as default value */
375 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
376 /* Set MU NDPA rate & BW source */
377 rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER);
378 /* Set NDPA Rate */
379 rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate);
380
381 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE,
382 DESC_RATE6M);
383 }
384 EXPORT_SYMBOL(rtw_bf_phy_init);
385
rtw_bf_cfg_csi_rate(struct rtw_dev * rtwdev,u8 rssi,u8 cur_rate,u8 fixrate_en,u8 * new_rate)386 void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
387 u8 fixrate_en, u8 *new_rate)
388 {
389 u32 csi_cfg;
390 u16 cur_rrsr;
391
392 csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE;
393 cur_rrsr = rtw_read16(rtwdev, REG_RRSR);
394
395 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C)
396 csi_cfg |= BIT_CSI_FORCE_RATE;
397
398 if (rssi >= 40) {
399 if (cur_rate != DESC_RATE54M) {
400 cur_rrsr |= BIT(DESC_RATE54M);
401 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
402 BIT_SHIFT_CSI_RATE;
403 rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
404 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
405 }
406 *new_rate = DESC_RATE54M;
407 } else {
408 if (cur_rate != DESC_RATE24M) {
409 cur_rrsr &= ~BIT(DESC_RATE54M);
410 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
411 BIT_SHIFT_CSI_RATE;
412 rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
413 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
414 }
415 *new_rate = DESC_RATE24M;
416 }
417 }
418 EXPORT_SYMBOL(rtw_bf_cfg_csi_rate);
419