1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ADF4350/ADF4351 SPI Wideband Synthesizer driver
4 *
5 * Copyright 2012-2013 Analog Devices Inc.
6 */
7
8 #include <linux/device.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/property.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/gcd.h>
18 #include <linux/gpio/consumer.h>
19 #include <asm/div64.h>
20 #include <linux/clk.h>
21 #include <linux/clk-provider.h>
22
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/frequency/adf4350.h>
26
27 enum {
28 ADF4350_FREQ,
29 ADF4350_FREQ_REFIN,
30 ADF4350_FREQ_RESOLUTION,
31 ADF4350_PWRDOWN,
32 };
33
34 struct adf4350_state {
35 struct spi_device *spi;
36 struct gpio_desc *lock_detect_gpiod;
37 struct adf4350_platform_data *pdata;
38 struct clk *clk;
39 struct clk *clkout;
40 const char *clk_out_name;
41 struct clk_hw hw;
42 unsigned long clkin;
43 unsigned long chspc; /* Channel Spacing */
44 unsigned long fpfd; /* Phase Frequency Detector */
45 unsigned long min_out_freq;
46 unsigned r0_fract;
47 unsigned r0_int;
48 unsigned r1_mod;
49 unsigned r4_rf_div_sel;
50 unsigned long regs[6];
51 unsigned long regs_hw[6];
52 unsigned long long freq_req;
53 /*
54 * Lock to protect the state of the device from potential concurrent
55 * writes. The device is configured via a sequence of SPI writes,
56 * and this lock is meant to prevent the start of another sequence
57 * before another one has finished.
58 */
59 struct mutex lock;
60 /*
61 * DMA (thus cache coherency maintenance) may require that
62 * transfer buffers live in their own cache lines.
63 */
64 __be32 val __aligned(IIO_DMA_MINALIGN);
65 };
66
67 #define to_adf4350_state(_hw) container_of(_hw, struct adf4350_state, hw)
68
69 static struct adf4350_platform_data default_pdata = {
70 .channel_spacing = 10000,
71 .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
72 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
73 .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
74 .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
75 ADF4350_REG4_MUTE_TILL_LOCK_EN,
76 };
77
adf4350_sync_config(struct adf4350_state * st)78 static int adf4350_sync_config(struct adf4350_state *st)
79 {
80 int ret, i, doublebuf = 0;
81
82 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
83 if ((st->regs_hw[i] != st->regs[i]) ||
84 ((i == ADF4350_REG0) && doublebuf)) {
85 switch (i) {
86 case ADF4350_REG1:
87 case ADF4350_REG4:
88 doublebuf = 1;
89 break;
90 }
91
92 st->val = cpu_to_be32(st->regs[i] | i);
93 ret = spi_write(st->spi, &st->val, 4);
94 if (ret < 0)
95 return ret;
96 st->regs_hw[i] = st->regs[i];
97 dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
98 i, (u32)st->regs[i] | i);
99 }
100 }
101 return 0;
102 }
103
adf4350_reg_access(struct iio_dev * indio_dev,unsigned reg,unsigned writeval,unsigned * readval)104 static int adf4350_reg_access(struct iio_dev *indio_dev,
105 unsigned reg, unsigned writeval,
106 unsigned *readval)
107 {
108 struct adf4350_state *st = iio_priv(indio_dev);
109 int ret;
110
111 if (reg > ADF4350_REG5)
112 return -EINVAL;
113
114 mutex_lock(&st->lock);
115 if (readval == NULL) {
116 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
117 ret = adf4350_sync_config(st);
118 } else {
119 *readval = st->regs_hw[reg];
120 ret = 0;
121 }
122 mutex_unlock(&st->lock);
123
124 return ret;
125 }
126
adf4350_tune_r_cnt(struct adf4350_state * st,unsigned short r_cnt)127 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
128 {
129 struct adf4350_platform_data *pdata = st->pdata;
130
131 do {
132 r_cnt++;
133 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
134 (r_cnt * (pdata->ref_div2_en ? 2 : 1));
135 } while (st->fpfd > ADF4350_MAX_FREQ_PFD);
136
137 return r_cnt;
138 }
139
adf4350_set_freq(struct adf4350_state * st,unsigned long long freq)140 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
141 {
142 struct adf4350_platform_data *pdata = st->pdata;
143 u64 tmp;
144 u32 div_gcd, prescaler, chspc;
145 u16 mdiv, r_cnt = 0;
146 u8 band_sel_div;
147
148 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
149 return -EINVAL;
150
151 st->r4_rf_div_sel = 0;
152
153 /*
154 * NOTE: This iteratively shifts freq by a power of 2
155 * (st->r4_rf_div_sel) to meet or exceed ADF4350_MIN_VCO_FREQ.
156 * A constant-time approach using fls_long() was attempted but
157 * deemed more complex without meaningful benefit for init code.
158 */
159 while (freq < ADF4350_MIN_VCO_FREQ) {
160 freq <<= 1;
161 st->r4_rf_div_sel++;
162 }
163
164 if (freq > ADF4350_MAX_FREQ_45_PRESC) {
165 prescaler = ADF4350_REG1_PRESCALER;
166 mdiv = 75;
167 } else {
168 prescaler = 0;
169 mdiv = 23;
170 }
171
172 /*
173 * Allow a predefined reference division factor
174 * if not set, compute our own
175 */
176 if (pdata->ref_div_factor)
177 r_cnt = pdata->ref_div_factor - 1;
178
179 chspc = st->chspc;
180
181 do {
182 do {
183 do {
184 r_cnt = adf4350_tune_r_cnt(st, r_cnt);
185 st->r1_mod = st->fpfd / chspc;
186 if (r_cnt > ADF4350_MAX_R_CNT) {
187 /* try higher spacing values */
188 chspc++;
189 r_cnt = 0;
190 }
191 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
192 } while (r_cnt == 0);
193
194 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
195 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
196 st->r0_fract = do_div(tmp, st->r1_mod);
197 st->r0_int = tmp;
198 } while (mdiv > st->r0_int);
199
200 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
201
202 if (st->r0_fract && st->r1_mod) {
203 div_gcd = gcd(st->r1_mod, st->r0_fract);
204 st->r1_mod /= div_gcd;
205 st->r0_fract /= div_gcd;
206 } else {
207 st->r0_fract = 0;
208 st->r1_mod = 1;
209 }
210
211 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
212 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
213 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
214 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
215 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
216 band_sel_div);
217
218 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
219 ADF4350_REG0_FRACT(st->r0_fract);
220
221 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
222 ADF4350_REG1_MOD(st->r1_mod) |
223 prescaler;
224
225 st->regs[ADF4350_REG2] =
226 ADF4350_REG2_10BIT_R_CNT(r_cnt) |
227 ADF4350_REG2_DOUBLE_BUFF_EN |
228 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
229 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
230 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
231 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
232 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
233 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
234
235 st->regs[ADF4350_REG3] = pdata->r3_user_settings &
236 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
237 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
238 ADF4350_REG3_12BIT_CSR_EN |
239 ADF4351_REG3_CHARGE_CANCELLATION_EN |
240 ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
241 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
242
243 st->regs[ADF4350_REG4] =
244 ADF4350_REG4_FEEDBACK_FUND |
245 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
246 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
247 ADF4350_REG4_RF_OUT_EN |
248 (pdata->r4_user_settings &
249 (ADF4350_REG4_OUTPUT_PWR(0x3) |
250 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
251 ADF4350_REG4_AUX_OUTPUT_EN |
252 ADF4350_REG4_AUX_OUTPUT_FUND |
253 ADF4350_REG4_MUTE_TILL_LOCK_EN));
254
255 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
256 st->freq_req = freq;
257
258 return adf4350_sync_config(st);
259 }
260
adf4350_write(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)261 static ssize_t adf4350_write(struct iio_dev *indio_dev,
262 uintptr_t private,
263 const struct iio_chan_spec *chan,
264 const char *buf, size_t len)
265 {
266 struct adf4350_state *st = iio_priv(indio_dev);
267 unsigned long long readin;
268 unsigned long tmp;
269 int ret;
270
271 ret = kstrtoull(buf, 10, &readin);
272 if (ret)
273 return ret;
274
275 mutex_lock(&st->lock);
276 switch ((u32)private) {
277 case ADF4350_FREQ:
278 ret = adf4350_set_freq(st, readin);
279 break;
280 case ADF4350_FREQ_REFIN:
281 if (readin > ADF4350_MAX_FREQ_REFIN) {
282 ret = -EINVAL;
283 break;
284 }
285
286 if (st->clk) {
287 tmp = clk_round_rate(st->clk, readin);
288 if (tmp != readin) {
289 ret = -EINVAL;
290 break;
291 }
292 ret = clk_set_rate(st->clk, tmp);
293 if (ret < 0)
294 break;
295 }
296 st->clkin = readin;
297 ret = adf4350_set_freq(st, st->freq_req);
298 break;
299 case ADF4350_FREQ_RESOLUTION:
300 if (readin == 0)
301 ret = -EINVAL;
302 else
303 st->chspc = readin;
304 break;
305 case ADF4350_PWRDOWN:
306 if (readin)
307 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
308 else
309 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
310
311 adf4350_sync_config(st);
312 break;
313 default:
314 ret = -EINVAL;
315 }
316 mutex_unlock(&st->lock);
317
318 return ret ? ret : len;
319 }
320
adf4350_read(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)321 static ssize_t adf4350_read(struct iio_dev *indio_dev,
322 uintptr_t private,
323 const struct iio_chan_spec *chan,
324 char *buf)
325 {
326 struct adf4350_state *st = iio_priv(indio_dev);
327 unsigned long long val;
328 int ret = 0;
329
330 mutex_lock(&st->lock);
331 switch ((u32)private) {
332 case ADF4350_FREQ:
333 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
334 (u64)st->fpfd;
335 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
336 /* PLL unlocked? return error */
337 if (st->lock_detect_gpiod)
338 if (!gpiod_get_value(st->lock_detect_gpiod)) {
339 dev_dbg(&st->spi->dev, "PLL un-locked\n");
340 ret = -EBUSY;
341 }
342 break;
343 case ADF4350_FREQ_REFIN:
344 if (st->clk)
345 st->clkin = clk_get_rate(st->clk);
346
347 val = st->clkin;
348 break;
349 case ADF4350_FREQ_RESOLUTION:
350 val = st->chspc;
351 break;
352 case ADF4350_PWRDOWN:
353 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
354 break;
355 default:
356 ret = -EINVAL;
357 val = 0;
358 }
359 mutex_unlock(&st->lock);
360
361 return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
362 }
363
364 #define _ADF4350_EXT_INFO(_name, _ident) { \
365 .name = _name, \
366 .read = adf4350_read, \
367 .write = adf4350_write, \
368 .private = _ident, \
369 .shared = IIO_SEPARATE, \
370 }
371
372 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
373 /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
374 * values > 2^32 in order to support the entire frequency range
375 * in Hz. Using scale is a bit ugly.
376 */
377 _ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
378 _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
379 _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
380 _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
381 { }
382 };
383
384 static const struct iio_chan_spec adf4350_chan = {
385 .type = IIO_ALTVOLTAGE,
386 .indexed = 1,
387 .output = 1,
388 .ext_info = adf4350_ext_info,
389 };
390
391 static const struct iio_info adf4350_info = {
392 .debugfs_reg_access = &adf4350_reg_access,
393 };
394
adf4350_clk_del_provider(void * data)395 static void adf4350_clk_del_provider(void *data)
396 {
397 struct adf4350_state *st = data;
398
399 of_clk_del_provider(st->spi->dev.of_node);
400 }
401
adf4350_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)402 static unsigned long adf4350_clk_recalc_rate(struct clk_hw *hw,
403 unsigned long parent_rate)
404 {
405 struct adf4350_state *st = to_adf4350_state(hw);
406 unsigned long long tmp;
407
408 tmp = (u64)(st->r0_int * st->r1_mod + st->r0_fract) * st->fpfd;
409 do_div(tmp, st->r1_mod * (1 << st->r4_rf_div_sel));
410
411 return tmp;
412 }
413
adf4350_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)414 static int adf4350_clk_set_rate(struct clk_hw *hw,
415 unsigned long rate,
416 unsigned long parent_rate)
417 {
418 struct adf4350_state *st = to_adf4350_state(hw);
419
420 if (parent_rate == 0 || parent_rate > ADF4350_MAX_FREQ_REFIN)
421 return -EINVAL;
422
423 st->clkin = parent_rate;
424
425 return adf4350_set_freq(st, rate);
426 }
427
adf4350_clk_prepare(struct clk_hw * hw)428 static int adf4350_clk_prepare(struct clk_hw *hw)
429 {
430 struct adf4350_state *st = to_adf4350_state(hw);
431
432 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
433
434 return adf4350_sync_config(st);
435 }
436
adf4350_clk_unprepare(struct clk_hw * hw)437 static void adf4350_clk_unprepare(struct clk_hw *hw)
438 {
439 struct adf4350_state *st = to_adf4350_state(hw);
440
441 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
442
443 adf4350_sync_config(st);
444 }
445
adf4350_clk_is_enabled(struct clk_hw * hw)446 static int adf4350_clk_is_enabled(struct clk_hw *hw)
447 {
448 struct adf4350_state *st = to_adf4350_state(hw);
449
450 return (st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
451 }
452
453 static const struct clk_ops adf4350_clk_ops = {
454 .recalc_rate = adf4350_clk_recalc_rate,
455 .set_rate = adf4350_clk_set_rate,
456 .prepare = adf4350_clk_prepare,
457 .unprepare = adf4350_clk_unprepare,
458 .is_enabled = adf4350_clk_is_enabled,
459 };
460
adf4350_clk_register(struct adf4350_state * st)461 static int adf4350_clk_register(struct adf4350_state *st)
462 {
463 struct spi_device *spi = st->spi;
464 struct clk_init_data init;
465 struct clk *clk;
466 const char *parent_name;
467 int ret;
468
469 if (!device_property_present(&spi->dev, "#clock-cells"))
470 return 0;
471
472 if (device_property_read_string(&spi->dev, "clock-output-names", &init.name)) {
473 init.name = devm_kasprintf(&spi->dev, GFP_KERNEL, "%s-clk",
474 fwnode_get_name(dev_fwnode(&spi->dev)));
475 if (!init.name)
476 return -ENOMEM;
477 }
478
479 parent_name = of_clk_get_parent_name(spi->dev.of_node, 0);
480 if (!parent_name)
481 return -EINVAL;
482
483 init.ops = &adf4350_clk_ops;
484 init.parent_names = &parent_name;
485 init.num_parents = 1;
486 init.flags = CLK_SET_RATE_PARENT;
487
488 st->hw.init = &init;
489 clk = devm_clk_register(&spi->dev, &st->hw);
490 if (IS_ERR(clk))
491 return PTR_ERR(clk);
492
493 ret = of_clk_add_provider(spi->dev.of_node, of_clk_src_simple_get, clk);
494 if (ret)
495 return ret;
496
497 st->clkout = clk;
498
499 return devm_add_action_or_reset(&spi->dev, adf4350_clk_del_provider, st);
500 }
501
adf4350_parse_dt(struct device * dev)502 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
503 {
504 struct adf4350_platform_data *pdata;
505 unsigned int tmp;
506
507 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
508 if (!pdata)
509 return NULL;
510
511 snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev));
512
513 tmp = 10000;
514 device_property_read_u32(dev, "adi,channel-spacing", &tmp);
515 pdata->channel_spacing = tmp;
516
517 tmp = 0;
518 device_property_read_u32(dev, "adi,power-up-frequency", &tmp);
519 pdata->power_up_frequency = tmp;
520
521 tmp = 0;
522 device_property_read_u32(dev, "adi,reference-div-factor", &tmp);
523 pdata->ref_div_factor = tmp;
524
525 pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable");
526 pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable");
527
528 /* r2_user_settings */
529 pdata->r2_user_settings = 0;
530 if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable"))
531 pdata->r2_user_settings |= ADF4350_REG2_PD_POLARITY_POS;
532 if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable"))
533 pdata->r2_user_settings |= ADF4350_REG2_LDP_6ns;
534 if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable"))
535 pdata->r2_user_settings |= ADF4350_REG2_LDF_INT_N;
536
537 tmp = 2500;
538 device_property_read_u32(dev, "adi,charge-pump-current", &tmp);
539 pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);
540
541 tmp = 0;
542 device_property_read_u32(dev, "adi,muxout-select", &tmp);
543 pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp);
544
545 if (device_property_read_bool(dev, "adi,low-spur-mode-enable"))
546 pdata->r2_user_settings |= ADF4350_REG2_NOISE_MODE(0x3);
547
548 /* r3_user_settings */
549
550 pdata->r3_user_settings = 0;
551 if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable"))
552 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CSR_EN;
553 if (device_property_read_bool(dev, "adi,charge-cancellation-enable"))
554 pdata->r3_user_settings |= ADF4351_REG3_CHARGE_CANCELLATION_EN;
555 if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable"))
556 pdata->r3_user_settings |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN;
557 if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable"))
558 pdata->r3_user_settings |= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH;
559
560 tmp = 0;
561 device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp);
562 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp);
563
564 tmp = 0;
565 device_property_read_u32(dev, "adi,clk-divider-mode", &tmp);
566 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);
567
568 /* r4_user_settings */
569
570 pdata->r4_user_settings = 0;
571 if (device_property_read_bool(dev, "adi,aux-output-enable"))
572 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_EN;
573 if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable"))
574 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_FUND;
575 if (device_property_read_bool(dev, "adi,mute-till-lock-enable"))
576 pdata->r4_user_settings |= ADF4350_REG4_MUTE_TILL_LOCK_EN;
577
578 tmp = 0;
579 device_property_read_u32(dev, "adi,output-power", &tmp);
580 pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp);
581
582 tmp = 0;
583 device_property_read_u32(dev, "adi,aux-output-power", &tmp);
584 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);
585
586 return pdata;
587 }
588
adf4350_power_down(void * data)589 static void adf4350_power_down(void *data)
590 {
591 struct iio_dev *indio_dev = data;
592 struct adf4350_state *st = iio_priv(indio_dev);
593
594 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
595 adf4350_sync_config(st);
596 }
597
adf4350_probe(struct spi_device * spi)598 static int adf4350_probe(struct spi_device *spi)
599 {
600 struct adf4350_platform_data *pdata;
601 struct iio_dev *indio_dev;
602 struct adf4350_state *st;
603 struct clk *clk = NULL;
604 int ret;
605
606 if (dev_fwnode(&spi->dev)) {
607 pdata = adf4350_parse_dt(&spi->dev);
608 if (pdata == NULL)
609 return -ENOMEM;
610 } else {
611 pdata = dev_get_platdata(&spi->dev);
612 }
613
614 if (!pdata) {
615 dev_warn(&spi->dev, "no platform data? using default\n");
616 pdata = &default_pdata;
617 }
618
619 if (!pdata->clkin) {
620 clk = devm_clk_get_enabled(&spi->dev, "clkin");
621 if (IS_ERR(clk))
622 return PTR_ERR(clk);
623 }
624
625 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
626 if (indio_dev == NULL)
627 return -ENOMEM;
628
629 st = iio_priv(indio_dev);
630
631 ret = devm_regulator_get_enable(&spi->dev, "vcc");
632 if (ret)
633 return ret;
634
635 st->spi = spi;
636 st->pdata = pdata;
637
638 indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
639 spi_get_device_id(spi)->name;
640
641 indio_dev->info = &adf4350_info;
642 indio_dev->modes = INDIO_DIRECT_MODE;
643
644 mutex_init(&st->lock);
645
646 st->chspc = pdata->channel_spacing;
647 if (clk) {
648 st->clk = clk;
649 st->clkin = clk_get_rate(clk);
650 } else {
651 st->clkin = pdata->clkin;
652 }
653
654 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
655 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
656
657 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
658
659 st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL,
660 GPIOD_IN);
661 if (IS_ERR(st->lock_detect_gpiod))
662 return PTR_ERR(st->lock_detect_gpiod);
663
664 if (pdata->power_up_frequency) {
665 ret = adf4350_set_freq(st, pdata->power_up_frequency);
666 if (ret)
667 return ret;
668 }
669
670 ret = adf4350_clk_register(st);
671 if (ret)
672 return ret;
673
674 if (!st->clkout) {
675 indio_dev->channels = &adf4350_chan;
676 indio_dev->num_channels = 1;
677 }
678
679 ret = devm_add_action_or_reset(&spi->dev, adf4350_power_down, indio_dev);
680 if (ret)
681 return ret;
682
683 return devm_iio_device_register(&spi->dev, indio_dev);
684 }
685
686 static const struct of_device_id adf4350_of_match[] = {
687 { .compatible = "adi,adf4350", },
688 { .compatible = "adi,adf4351", },
689 { }
690 };
691 MODULE_DEVICE_TABLE(of, adf4350_of_match);
692
693 static const struct spi_device_id adf4350_id[] = {
694 { .name = "adf4350", .driver_data = 4350 },
695 { .name = "adf4351", .driver_data = 4351 },
696 { }
697 };
698 MODULE_DEVICE_TABLE(spi, adf4350_id);
699
700 static struct spi_driver adf4350_driver = {
701 .driver = {
702 .name = "adf4350",
703 .of_match_table = adf4350_of_match,
704 },
705 .probe = adf4350_probe,
706 .id_table = adf4350_id,
707 };
708 module_spi_driver(adf4350_driver);
709
710 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
711 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
712 MODULE_LICENSE("GPL v2");
713