1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * NI 16550 UART Driver
4 *
5 * The National Instruments (NI) 16550 is a UART that is compatible with the
6 * TL16C550C and OX16C950B register interfaces, but has additional functions
7 * for RS-485 transceiver control. This driver implements support for the
8 * additional functionality on top of the standard serial8250 core.
9 *
10 * Copyright 2012-2023 National Instruments Corporation
11 */
12
13 #include <linux/bitfield.h>
14 #include <linux/bits.h>
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/io.h>
18 #include <linux/init.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/property.h>
23 #include <linux/serial_core.h>
24 #include <linux/types.h>
25
26 #include "8250.h"
27
28 /* Extra bits in UART_ACR */
29 #define NI16550_ACR_AUTO_DTR_EN BIT(4)
30
31 /* TFS - TX FIFO Size */
32 #define NI16550_TFS_OFFSET 0x0C
33 /* RFS - RX FIFO Size */
34 #define NI16550_RFS_OFFSET 0x0D
35
36 /* PMR - Port Mode Register */
37 #define NI16550_PMR_OFFSET 0x0E
38 /* PMR[1:0] - Port Capabilities */
39 #define NI16550_PMR_CAP_MASK GENMASK(1, 0)
40 #define NI16550_PMR_NOT_IMPL FIELD_PREP(NI16550_PMR_CAP_MASK, 0) /* not implemented */
41 #define NI16550_PMR_CAP_RS232 FIELD_PREP(NI16550_PMR_CAP_MASK, 1) /* RS-232 capable */
42 #define NI16550_PMR_CAP_RS485 FIELD_PREP(NI16550_PMR_CAP_MASK, 2) /* RS-485 capable */
43 #define NI16550_PMR_CAP_DUAL FIELD_PREP(NI16550_PMR_CAP_MASK, 3) /* dual-port */
44 /* PMR[4] - Interface Mode */
45 #define NI16550_PMR_MODE_MASK GENMASK(4, 4)
46 #define NI16550_PMR_MODE_RS232 FIELD_PREP(NI16550_PMR_MODE_MASK, 0) /* currently 232 */
47 #define NI16550_PMR_MODE_RS485 FIELD_PREP(NI16550_PMR_MODE_MASK, 1) /* currently 485 */
48
49 /* PCR - Port Control Register */
50 /*
51 * Wire Mode | Tx enabled? | Rx enabled?
52 * ---------------|----------------------|--------------------------
53 * PCR_RS422 | Always | Always
54 * PCR_ECHO_RS485 | When DTR asserted | Always
55 * PCR_DTR_RS485 | When DTR asserted | Disabled when TX enabled
56 * PCR_AUTO_RS485 | When data in TX FIFO | Disabled when TX enabled
57 */
58 #define NI16550_PCR_OFFSET 0x0F
59 #define NI16550_PCR_WIRE_MODE_MASK GENMASK(1, 0)
60 #define NI16550_PCR_RS422 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 0)
61 #define NI16550_PCR_ECHO_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 1)
62 #define NI16550_PCR_DTR_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 2)
63 #define NI16550_PCR_AUTO_RS485 FIELD_PREP(NI16550_PCR_WIRE_MODE_MASK, 3)
64 #define NI16550_PCR_TXVR_ENABLE_BIT BIT(3)
65 #define NI16550_PCR_RS485_TERMINATION_BIT BIT(6)
66
67 /* flags for ni16550_device_info */
68 #define NI_HAS_PMR BIT(0)
69
70 struct ni16550_device_info {
71 u32 uartclk;
72 u8 prescaler;
73 u8 flags;
74 };
75
76 struct ni16550_data {
77 int line;
78 struct clk *clk;
79 };
80
ni16550_enable_transceivers(struct uart_port * port)81 static int ni16550_enable_transceivers(struct uart_port *port)
82 {
83 u8 pcr;
84
85 pcr = port->serial_in(port, NI16550_PCR_OFFSET);
86 pcr |= NI16550_PCR_TXVR_ENABLE_BIT;
87 dev_dbg(port->dev, "enable transceivers: write pcr: 0x%02x\n", pcr);
88 port->serial_out(port, NI16550_PCR_OFFSET, pcr);
89
90 return 0;
91 }
92
ni16550_disable_transceivers(struct uart_port * port)93 static int ni16550_disable_transceivers(struct uart_port *port)
94 {
95 u8 pcr;
96
97 pcr = serial_port_in(port, NI16550_PCR_OFFSET);
98 pcr &= ~NI16550_PCR_TXVR_ENABLE_BIT;
99 dev_dbg(port->dev, "disable transceivers: write pcr: 0x%02x\n", pcr);
100 serial_port_out(port, NI16550_PCR_OFFSET, pcr);
101
102 return 0;
103 }
104
ni16550_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)105 static int ni16550_rs485_config(struct uart_port *port,
106 struct ktermios *termios,
107 struct serial_rs485 *rs485)
108 {
109 struct uart_8250_port *up = container_of(port, struct uart_8250_port, port);
110 u8 pcr;
111
112 pcr = serial_port_in(port, NI16550_PCR_OFFSET);
113 pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
114
115 if ((rs485->flags & SER_RS485_MODE_RS422) ||
116 !(rs485->flags & SER_RS485_ENABLED)) {
117 /* RS-422 */
118 pcr |= NI16550_PCR_RS422;
119 up->acr &= ~NI16550_ACR_AUTO_DTR_EN;
120 } else {
121 /* RS-485 2-wire Auto */
122 pcr |= NI16550_PCR_AUTO_RS485;
123 up->acr |= NI16550_ACR_AUTO_DTR_EN;
124 }
125
126 dev_dbg(port->dev, "config rs485: write pcr: 0x%02x, acr: %02x\n", pcr, up->acr);
127 serial_port_out(port, NI16550_PCR_OFFSET, pcr);
128 serial_icr_write(up, UART_ACR, up->acr);
129
130 return 0;
131 }
132
is_pmr_rs232_mode(struct uart_8250_port * up)133 static bool is_pmr_rs232_mode(struct uart_8250_port *up)
134 {
135 u8 pmr = serial_in(up, NI16550_PMR_OFFSET);
136 u8 pmr_mode = pmr & NI16550_PMR_MODE_MASK;
137 u8 pmr_cap = pmr & NI16550_PMR_CAP_MASK;
138
139 /*
140 * If the PMR is not implemented, then by default NI UARTs are
141 * connected to RS-485 transceivers
142 */
143 if (pmr_cap == NI16550_PMR_NOT_IMPL)
144 return false;
145
146 if (pmr_cap == NI16550_PMR_CAP_DUAL)
147 /*
148 * If the port is dual-mode capable, then read the mode bit
149 * to know the current mode
150 */
151 return pmr_mode == NI16550_PMR_MODE_RS232;
152 /*
153 * If it is not dual-mode capable, then decide based on the
154 * capability
155 */
156 return pmr_cap == NI16550_PMR_CAP_RS232;
157 }
158
ni16550_config_prescaler(struct uart_8250_port * up,u8 prescaler)159 static void ni16550_config_prescaler(struct uart_8250_port *up,
160 u8 prescaler)
161 {
162 /*
163 * Page in the Enhanced Mode Registers
164 * Sets EFR[4] for Enhanced Mode.
165 */
166 u8 lcr_value;
167 u8 efr_value;
168
169 lcr_value = serial_in(up, UART_LCR);
170 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
171
172 efr_value = serial_in(up, UART_EFR);
173 efr_value |= UART_EFR_ECB;
174
175 serial_out(up, UART_EFR, efr_value);
176
177 /* Page out the Enhanced Mode Registers */
178 serial_out(up, UART_LCR, lcr_value);
179
180 /* Set prescaler to CPR register. */
181 serial_out(up, UART_SCR, UART_CPR);
182 serial_out(up, UART_ICR, prescaler);
183 }
184
185 static const struct serial_rs485 ni16550_rs485_supported = {
186 .flags = SER_RS485_ENABLED | SER_RS485_MODE_RS422 | SER_RS485_RTS_ON_SEND |
187 SER_RS485_RTS_AFTER_SEND,
188 /*
189 * delay_rts_* and RX_DURING_TX are not supported.
190 *
191 * RTS_{ON,AFTER}_SEND are supported, but ignored; the transceiver
192 * is connected in only one way and we don't need userspace to tell
193 * us, but want to retain compatibility with applications that do.
194 */
195 };
196
ni16550_rs485_setup(struct uart_port * port)197 static void ni16550_rs485_setup(struct uart_port *port)
198 {
199 port->rs485_config = ni16550_rs485_config;
200 port->rs485_supported = ni16550_rs485_supported;
201 /*
202 * The hardware comes up by default in 2-wire auto mode and we
203 * set the flags to represent that
204 */
205 port->rs485.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
206 }
207
ni16550_port_startup(struct uart_port * port)208 static int ni16550_port_startup(struct uart_port *port)
209 {
210 int ret;
211
212 ret = serial8250_do_startup(port);
213 if (ret)
214 return ret;
215
216 return ni16550_enable_transceivers(port);
217 }
218
ni16550_port_shutdown(struct uart_port * port)219 static void ni16550_port_shutdown(struct uart_port *port)
220 {
221 ni16550_disable_transceivers(port);
222
223 serial8250_do_shutdown(port);
224 }
225
ni16550_get_regs(struct platform_device * pdev,struct uart_port * port)226 static int ni16550_get_regs(struct platform_device *pdev,
227 struct uart_port *port)
228 {
229 struct resource *regs;
230
231 regs = platform_get_mem_or_io(pdev, 0);
232 if (!regs)
233 return dev_err_probe(&pdev->dev, -EINVAL, "no registers defined\n");
234
235 switch (resource_type(regs)) {
236 case IORESOURCE_IO:
237 port->iotype = UPIO_PORT;
238 port->iobase = regs->start;
239
240 return 0;
241 case IORESOURCE_MEM:
242 port->iotype = UPIO_MEM;
243 port->mapbase = regs->start;
244 port->mapsize = resource_size(regs);
245 port->flags |= UPF_IOREMAP;
246
247 return 0;
248 default:
249 return -EINVAL;
250 }
251 }
252
253 /*
254 * Very old implementations don't have the TFS or RFS registers
255 * defined, so we may read all-0s or all-1s. For such devices,
256 * assume a FIFO size of 128.
257 */
ni16550_read_fifo_size(struct uart_8250_port * uart,int reg)258 static u8 ni16550_read_fifo_size(struct uart_8250_port *uart, int reg)
259 {
260 u8 value = serial_in(uart, reg);
261
262 if (value == 0x00 || value == 0xFF)
263 return 128;
264
265 return value;
266 }
267
ni16550_set_mctrl(struct uart_port * port,unsigned int mctrl)268 static void ni16550_set_mctrl(struct uart_port *port, unsigned int mctrl)
269 {
270 struct uart_8250_port *up = up_to_u8250p(port);
271
272 up->mcr |= UART_MCR_CLKSEL;
273 serial8250_do_set_mctrl(port, mctrl);
274 }
275
ni16550_probe(struct platform_device * pdev)276 static int ni16550_probe(struct platform_device *pdev)
277 {
278 const struct ni16550_device_info *info;
279 struct device *dev = &pdev->dev;
280 struct uart_8250_port uart = {};
281 unsigned int txfifosz, rxfifosz;
282 unsigned int prescaler;
283 struct ni16550_data *data;
284 const char *portmode;
285 bool rs232_property;
286 int ret;
287
288 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
289 if (!data)
290 return -ENOMEM;
291
292 spin_lock_init(&uart.port.lock);
293
294 ret = ni16550_get_regs(pdev, &uart.port);
295 if (ret < 0)
296 return ret;
297
298 /* early setup so that serial_in()/serial_out() work */
299 serial8250_set_defaults(&uart);
300
301 info = device_get_match_data(dev);
302
303 uart.port.dev = dev;
304 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_FIXED_TYPE;
305 uart.port.startup = ni16550_port_startup;
306 uart.port.shutdown = ni16550_port_shutdown;
307
308 /*
309 * Hardware instantiation of FIFO sizes are held in registers.
310 */
311 txfifosz = ni16550_read_fifo_size(&uart, NI16550_TFS_OFFSET);
312 rxfifosz = ni16550_read_fifo_size(&uart, NI16550_RFS_OFFSET);
313
314 dev_dbg(dev, "NI 16550 has TX FIFO size %u, RX FIFO size %u\n",
315 txfifosz, rxfifosz);
316
317 uart.port.type = PORT_16550A;
318 uart.port.fifosize = txfifosz;
319 uart.tx_loadsz = txfifosz;
320 uart.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
321 uart.capabilities = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR;
322
323 /*
324 * Declaration of the base clock frequency can come from one of:
325 * - static declaration in this driver (for older ACPI IDs)
326 * - a "clock-frequency" ACPI
327 */
328 uart.port.uartclk = info->uartclk;
329
330 ret = uart_read_port_properties(&uart.port);
331 if (ret)
332 return ret;
333
334 if (!uart.port.uartclk) {
335 data->clk = devm_clk_get_enabled(dev, NULL);
336 if (!IS_ERR(data->clk))
337 uart.port.uartclk = clk_get_rate(data->clk);
338 }
339
340 if (!uart.port.uartclk)
341 return dev_err_probe(dev, -ENODEV, "unable to determine clock frequency!\n");
342
343 prescaler = info->prescaler;
344 device_property_read_u32(dev, "clock-prescaler", &prescaler);
345 if (prescaler) {
346 uart.port.set_mctrl = ni16550_set_mctrl;
347 ni16550_config_prescaler(&uart, (u8)prescaler);
348 }
349
350 /*
351 * The determination of whether or not this is an RS-485 or RS-232 port
352 * can come from the PMR (if present), otherwise we're solely an RS-485
353 * port.
354 *
355 * This is a device-specific property, and there are old devices in the
356 * field using "transceiver" as an ACPI property, so we have to check
357 * for that as well.
358 */
359 if (!device_property_read_string(dev, "transceiver", &portmode)) {
360 rs232_property = strncmp(portmode, "RS-232", 6) == 0;
361
362 dev_dbg(dev, "port is in %s mode (via device property)\n",
363 rs232_property ? "RS-232" : "RS-485");
364 } else if (info->flags & NI_HAS_PMR) {
365 rs232_property = is_pmr_rs232_mode(&uart);
366
367 dev_dbg(dev, "port is in %s mode (via PMR)\n",
368 rs232_property ? "RS-232" : "RS-485");
369 } else {
370 rs232_property = 0;
371
372 dev_dbg(dev, "port is fixed as RS-485\n");
373 }
374
375 if (!rs232_property) {
376 /*
377 * Neither the 'transceiver' property nor the PMR indicate
378 * that this is an RS-232 port, so it must be an RS-485 one.
379 */
380 ni16550_rs485_setup(&uart.port);
381 }
382
383 ret = serial8250_register_8250_port(&uart);
384 if (ret < 0)
385 return ret;
386 data->line = ret;
387
388 platform_set_drvdata(pdev, data);
389 return 0;
390 }
391
ni16550_remove(struct platform_device * pdev)392 static void ni16550_remove(struct platform_device *pdev)
393 {
394 struct ni16550_data *data = platform_get_drvdata(pdev);
395
396 serial8250_unregister_port(data->line);
397 }
398
399 /* NI 16550 RS-485 Interface */
400 static const struct ni16550_device_info nic7750 = {
401 .uartclk = 33333333,
402 };
403
404 /* NI CVS-145x RS-485 Interface */
405 static const struct ni16550_device_info nic7772 = {
406 .uartclk = 1843200,
407 .flags = NI_HAS_PMR,
408 };
409
410 /* NI cRIO-904x RS-485 Interface */
411 static const struct ni16550_device_info nic792b = {
412 /* Sets UART clock rate to 22.222 MHz with 1.125 prescale */
413 .uartclk = 22222222,
414 .prescaler = 0x09,
415 };
416
417 /* NI sbRIO 96x8 RS-232/485 Interfaces */
418 static const struct ni16550_device_info nic7a69 = {
419 /* Set UART clock rate to 29.629 MHz with 1.125 prescale */
420 .uartclk = 29629629,
421 .prescaler = 0x09,
422 };
423
424 static const struct acpi_device_id ni16550_acpi_match[] = {
425 { "NIC7750", (kernel_ulong_t)&nic7750 },
426 { "NIC7772", (kernel_ulong_t)&nic7772 },
427 { "NIC792B", (kernel_ulong_t)&nic792b },
428 { "NIC7A69", (kernel_ulong_t)&nic7a69 },
429 { }
430 };
431 MODULE_DEVICE_TABLE(acpi, ni16550_acpi_match);
432
433 static struct platform_driver ni16550_driver = {
434 .driver = {
435 .name = "ni16550",
436 .acpi_match_table = ni16550_acpi_match,
437 },
438 .probe = ni16550_probe,
439 .remove = ni16550_remove,
440 };
441
442 module_platform_driver(ni16550_driver);
443
444 MODULE_AUTHOR("Emerson Electric Co.");
445 MODULE_DESCRIPTION("NI 16550 Driver");
446 MODULE_LICENSE("GPL");
447