1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef __SOF_AMD_ACP_H 12 #define __SOF_AMD_ACP_H 13 14 #include <linux/dmi.h> 15 #include <linux/soundwire/sdw_amd.h> 16 #include "../sof-priv.h" 17 #include "../sof-audio.h" 18 19 #define ACP_MAX_STREAM 8 20 21 #define ACP_DSP_BAR 0 22 23 #define ACP_HW_SEM_RETRY_COUNT 10000 24 #define ACP_REG_POLL_INTERVAL 500 25 #define ACP_REG_POLL_TIMEOUT_US 2000 26 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000 27 28 #define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01 29 #define ACP3X_PGFSM_STATUS_MASK 0x03 30 #define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07 31 #define ACP6X_PGFSM_STATUS_MASK 0x0F 32 #define ACP70_PGFSM_CNTL_POWER_ON_MASK 0x1F 33 #define ACP70_PGFSM_STATUS_MASK 0xFF 34 35 #define ACP_POWERED_ON 0x00 36 #define ACP_ASSERT_RESET 0x01 37 #define ACP_RELEASE_RESET 0x00 38 #define ACP_SOFT_RESET_DONE_MASK 0x00010001 39 #define ACP_DSP_ASSERT_RESET 0x04 40 #define ACP_DSP_RELEASE_RESET 0x00 41 #define ACP_DSP_SOFT_RESET_DONE_MASK 0x00050004 42 43 #define ACP_DSP_INTR_EN_MASK 0x00000001 44 #define ACP3X_SRAM_PTE_OFFSET 0x02050000 45 #define ACP5X_SRAM_PTE_OFFSET 0x02050000 46 #define ACP6X_SRAM_PTE_OFFSET 0x03800000 47 #define ACP70_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET 48 #define PAGE_SIZE_4K_ENABLE 0x2 49 #define ACP_PAGE_SIZE 0x1000 50 #define ACP_DMA_CH_RUN 0x02 51 #define ACP_MAX_DESC_CNT 0x02 52 #define ACP_DSP_RUN 0x00 53 #define DSP_FW_RUN_ENABLE 0x01 54 #define ACP_SHA_RUN 0x01 55 #define ACP_SHA_RESET 0x02 56 #define ACP_SHA_HEADER 0x01 57 /* SHA_IOC_En (bit 2): interrupt-on-completion to ASP; must be set alongside sha_run */ 58 #define ACP_SHA_IOC_EN 0x04 59 #define ACP_SHA_RUN_WITH_IOC (ACP_SHA_RUN | ACP_SHA_IOC_EN) 60 #define ACP_DMA_CH_RST 0x01 61 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10 62 #define ACP_ATU_CACHE_INVALID 0x01 63 #define ACP_MAX_DESC 128 64 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0 65 66 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000 67 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 68 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 69 #define ACP_IRAM_BASE_ADDRESS 0x000000 70 #define ACP_DRAM_BASE_ADDRESS 0x01000000 71 #define ACP_DRAM_PAGE_COUNT 128 72 #define ACP_SRAM_BASE_ADDRESS 0x3806000 73 #define ACP7X_SRAM_BASE_ADDRESS 0x380C000 74 #define ACP_DSP_TO_HOST_IRQ 0x04 75 76 #define ACP_RN_PCI_ID 0x01 77 #define ACP_VANGOGH_PCI_ID 0x50 78 #define ACP_RMB_PCI_ID 0x6F 79 #define ACP63_PCI_ID 0x63 80 #define ACP70_PCI_ID 0x70 81 #define ACP71_PCI_ID 0x71 82 #define ACP72_PCI_ID 0x72 83 #define ACP7B_PCI_ID 0x7B 84 #define ACP7F_PCI_ID 0x7F 85 86 #define ACP7X_PGFSM_CNTL_POWER_ON_MASK 0x7F 87 #define ACP7X_PGFSM_STATUS_MASK 0xFFF 88 #define ACP7X_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET 89 90 #define HOST_BRIDGE_CZN 0x1630 91 #define HOST_BRIDGE_VGH 0x1645 92 #define HOST_BRIDGE_RMB 0x14B5 93 #define HOST_BRIDGE_ACP63 0x14E8 94 #define HOST_BRIDGE_ACP70 0x1507 95 #define ACP_SHA_STAT 0x8000 96 #define ACP_PSP_TIMEOUT_US 1000000 97 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 98 #define MP0_C2PMSG_114_REG 0x3810AC8 99 #define MP0_C2PMSG_73_REG 0x3810A24 100 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000 101 #define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000 102 #define MBOX_DELAY_US 1000 103 #define MBOX_READY_MASK 0x80000000 104 #define MBOX_STATUS_MASK 0xFFFF 105 #define MBOX_ISREADY_FLAG 0x40000000 106 #define IRAM_DRAM_FENCE_0 0X0 107 #define IRAM_DRAM_FENCE_1 0X01 108 #define IRAM_DRAM_FENCE_2 0X02 109 110 #define BOX_SIZE_512 0x200 111 #define BOX_SIZE_1024 0x400 112 113 #define EXCEPT_MAX_HDR_SIZE 0x400 114 #define AMD_STACK_DUMP_SIZE 32 115 116 #define SRAM1_SIZE 0x280000 117 #define PROBE_STATUS_BIT BIT(31) 118 119 #define ACP_FIRMWARE_SIGNATURE 0x100 120 #define ACP_IMAGE_HEADER_SIZE ACP_FIRMWARE_SIGNATURE 121 #define ACP_IMAGE_HDR_SIZE_FW_SIGNED_OFF 0x14 122 #define ACP_ASP_SIGNATURE_LENGTH 512 123 124 /* 125 * ACP7.B/7.F carveout: 32 MB region mapped at 2 MB page granularity. 126 * Use AXI2AXIATU_PAGE_SIZE_Mask2MB (value 0x0) for carveout ATU 127 * groups giving 32MB / 2MB = 16 PTEs. 4KB pages would require 8192 PTEs and 128 * is not how the hardware carveout path is configured. 129 */ 130 #define ACP7X_CARVEOUT_MAX_SIZE (32 * SZ_1M) 131 #define ACP7X_CARVEOUT_PAGE_SIZE (2 * SZ_1M) 132 #define ACP7X_CARVEOUT_PAGE_COUNT (ACP7X_CARVEOUT_MAX_SIZE / ACP7X_CARVEOUT_PAGE_SIZE) 133 /* 134 * PTE high-word flags for ATU entries: 135 * bit[31]: PAGE_Enable - entry is valid 136 * bit[30]: MALL_Enable - route accesses through carveout (MALL) memory, 137 * not standard DRAM. Required for ASP to recognise the SHA DMA 138 * source as within the carveout and grant ACP_SHA_DSP_FW_QUALIFIER. 139 * (PAGE_Enable | MALL_Enable ATU entry flags) 140 */ 141 #define ACP_ATU_PTE_PAGE_ENABLE BIT(31) 142 #define ACP_ATU_PTE_MALL_ENABLE BIT(30) 143 #define ACP_ATU_PTE_CARVEOUT_FLAGS (ACP_ATU_PTE_PAGE_ENABLE | ACP_ATU_PTE_MALL_ENABLE) 144 145 #define ACP_ERROR_IRQ_MASK BIT(29) 146 #define ACP_SDW0_IRQ_MASK BIT(21) 147 #define ACP_SDW1_IRQ_MASK BIT(2) 148 #define SDW_ACPI_ADDR_ACP63 5 149 #define SDW_ACPI_ADDR_ACP70 SDW_ACPI_ADDR_ACP63 150 #define ACP_DEFAULT_SRAM_LENGTH 0x00080000 151 #define ACP_SRAM_PAGE_COUNT 128 152 #define ACP6X_SDW_MAX_MANAGER_COUNT 2 153 #define ACP70_SDW_MAX_MANAGER_COUNT ACP6X_SDW_MAX_MANAGER_COUNT 154 /* ACPI _DSD acp-audio-ep-port values for PDM controller selection */ 155 #define ACP_DEV_PORT_PDM 4 156 #define ACP_DEV_PORT_PDM2 5 157 #define SDW_ACPI_ADDR_ACP7X SDW_ACPI_ADDR_ACP63 158 #define ACP7X_SDW_MAX_MANAGER_COUNT 4 159 160 /* ACPI child device address for the ACP7x PDM/DMIC device */ 161 #define ACP7X_DMIC_ADDR 2 162 #define ACP_DSP_MSG_SET 1 163 #define ACP_DSP_ACK_SET 1 164 165 /* 166 * ATU PTE group ACP logical address offsets. 167 * Each group covers 8 MB (0x00800000). Groups 1-8 are used for PCM 168 * streams; groups 9-16 are extended groups. 169 * 170 * GRP_N_OFFSET = (N - 1) * 8 MB 171 */ 172 #define PTE_GRP1_OFFSET 0x00000000 173 #define PTE_GRP2_OFFSET 0x00800000 174 #define PTE_GRP3_OFFSET 0x01000000 175 #define PTE_GRP4_OFFSET 0x01800000 176 #define PTE_GRP5_OFFSET 0x02000000 177 #define PTE_GRP6_OFFSET 0x02800000 178 #define PTE_GRP7_OFFSET 0x03000000 179 #define PTE_GRP8_OFFSET 0x03800000 180 #define PTE_GRP9_OFFSET 0x04000000 181 #define PTE_GRP10_OFFSET 0x04800000 182 #define PTE_GRP11_OFFSET 0x05000000 183 #define PTE_GRP12_OFFSET 0x05800000 184 #define PTE_GRP13_OFFSET 0x06000000 185 #define PTE_GRP14_OFFSET 0x06800000 186 #define PTE_GRP15_OFFSET 0x07000000 187 #define PTE_GRP16_OFFSET 0x07800000 188 189 enum clock_source { 190 ACP_CLOCK_96M = 0, 191 ACP_CLOCK_48M, 192 ACP_CLOCK_24M, 193 ACP_CLOCK_ACLK, 194 ACP_CLOCK_MCLK, 195 }; 196 197 struct acp_atu_grp_pte { 198 u32 low; 199 u32 high; 200 }; 201 202 /* ASP mailbox payload for GET_CARVEOUT_ADDR command (0x04) */ 203 struct asp_get_carveout_payload { 204 u32 cookie; /* [0x00] Driver: ASP_MBOX_COOKIE */ 205 u32 status; /* [0x04] ASP: 0 = success */ 206 u64 carveout_addr; /* [0x08] ASP: carveout physical base address */ 207 u32 carveout_size; /* [0x10] ASP: ACP_MALL_SIZE register value */ 208 u32 mall_addr_valid; /* [0x14] ASP: ACP_MALL_ADDR_VALID register value */ 209 u32 mall_valid; /* [0x18] ASP: ACP_MALL_VALID register value */ 210 }; 211 212 /* 213 * ASP mailbox payload for VALIDATE_IMAGE command (0x01). 214 * Driver fills src/dest fields; ASP fills carveout_dest_addr and status. 215 */ 216 struct asp_validate_image_payload { 217 u32 cookie; /* [0x00] Driver: ASP_MBOX_COOKIE */ 218 u32 status; /* [0x04] ASP: 0 = success */ 219 u64 carveout_dest_addr; /* [0x08] ASP: physical addr of raw binary in carveout */ 220 u64 dest_offset; /* [0x10] Driver: destination offset within carveout */ 221 u64 src_phys_addr; /* [0x18] Driver: signed FW source physical addr in DDR */ 222 u32 fw_image_size; /* [0x20] Driver: total signed image size in bytes */ 223 }; 224 225 union dma_tx_cnt { 226 struct { 227 unsigned int count : 19; 228 unsigned int reserved : 12; 229 unsigned ioc : 1; 230 } bitfields, bits; 231 unsigned int u32_all; 232 signed int i32_all; 233 }; 234 235 struct dma_descriptor { 236 unsigned int src_addr; 237 unsigned int dest_addr; 238 union dma_tx_cnt tx_cnt; 239 unsigned int reserved; 240 }; 241 242 /* Scratch memory structure for communication b/w host and dsp */ 243 struct scratch_ipc_conf { 244 /* Debug memory */ 245 u8 sof_debug_box[1024]; 246 /* Exception memory*/ 247 u8 sof_except_box[1024]; 248 /* Stream buffer */ 249 u8 sof_stream_box[1024]; 250 /* Trace buffer */ 251 u8 sof_trace_box[1024]; 252 /* Host msg flag */ 253 u32 sof_host_msg_write; 254 /* Host ack flag*/ 255 u32 sof_host_ack_write; 256 /* DSP msg flag */ 257 u32 sof_dsp_msg_write; 258 /* Dsp ack flag */ 259 u32 sof_dsp_ack_write; 260 }; 261 262 struct scratch_reg_conf { 263 struct scratch_ipc_conf info; 264 struct acp_atu_grp_pte grp1_pte[16]; 265 struct acp_atu_grp_pte grp2_pte[16]; 266 struct acp_atu_grp_pte grp3_pte[16]; 267 struct acp_atu_grp_pte grp4_pte[16]; 268 struct acp_atu_grp_pte grp5_pte[16]; 269 struct acp_atu_grp_pte grp6_pte[16]; 270 struct acp_atu_grp_pte grp7_pte[16]; 271 struct acp_atu_grp_pte grp8_pte[16]; 272 struct dma_descriptor dma_desc[64]; 273 unsigned int reg_offset[8]; 274 unsigned int buf_size[8]; 275 u8 acp_tx_fifo_buf[256]; 276 u8 acp_rx_fifo_buf[256]; 277 unsigned int reserve[]; 278 }; 279 280 struct acp_dsp_stream { 281 struct list_head list; 282 struct snd_sof_dev *sdev; 283 struct snd_pcm_substream *substream; 284 struct snd_dma_buffer *dmab; 285 int num_pages; 286 int stream_tag; 287 int active; 288 unsigned int reg_offset; 289 size_t posn_offset; 290 struct snd_compr_stream *cstream; 291 u64 cstream_posn; 292 }; 293 294 struct sof_amd_acp_desc { 295 const char *name; 296 u32 pgfsm_base; 297 u32 ext_intr_enb; 298 u32 ext_intr_cntl; 299 u32 ext_intr_stat; 300 u32 ext_intr_stat1; 301 u32 dsp_intr_base; 302 u32 sram_pte_offset; 303 u32 hw_semaphore_offset; 304 u32 acp_clkmux_sel; 305 u32 fusion_dsp_offset; 306 u32 probe_reg_offset; 307 u32 reg_start_addr; 308 u32 reg_end_addr; 309 u32 acp_error_stat; 310 u32 acp_sw0_i2s_err_reason; 311 u32 sdw_max_link_count; 312 u64 sdw_acpi_dev_addr; 313 }; 314 315 struct acp_quirk_entry { 316 bool signed_fw_image; 317 bool skip_iram_dram_size_mod; 318 bool post_fw_run_delay; 319 }; 320 321 /* Common device data struct for ACP devices */ 322 struct acp_dev_data { 323 struct snd_sof_dev *dev; 324 const struct firmware *fw_dbin; 325 /* DMIC device */ 326 struct platform_device *dmic_dev; 327 /* mutex lock to protect ACP common registers access */ 328 struct mutex acp_lock; 329 /* ACPI information stored between scan and probe steps */ 330 struct sdw_amd_acpi_info info; 331 /* sdw context allocated by SoundWire driver */ 332 struct sdw_amd_ctx *sdw; 333 unsigned int fw_bin_size; 334 unsigned int fw_data_bin_size; 335 unsigned int fw_sram_data_bin_size; 336 const char *fw_code_bin; 337 const char *fw_data_bin; 338 const char *fw_sram_data_bin; 339 u32 fw_bin_page_count; 340 u32 fw_data_bin_page_count; 341 u32 addr; 342 u32 reg_range; 343 u32 blk_type; 344 dma_addr_t sha_dma_addr; 345 u8 *bin_buf; 346 dma_addr_t dma_addr; 347 u8 *data_buf; 348 dma_addr_t sram_dma_addr; 349 u8 *sram_data_buf; 350 struct acp_quirk_entry *quirks; 351 struct dma_descriptor dscr_info[ACP_MAX_DESC]; 352 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; 353 struct acp_dsp_stream *dtrace_stream; 354 struct acp_dsp_stream *probe_stream; 355 bool enable_fw_debug; 356 bool is_dram_in_use; 357 bool is_sram_in_use; 358 bool sdw_en_stat; 359 /* acp70_sdw0_wake_event flag set to true when wake irq asserted for SW0 instance */ 360 bool acp70_sdw0_wake_event; 361 /* acp70_sdw1_wake_event flag set to true when wake irq asserted for SW1 instance */ 362 bool acp70_sdw1_wake_event; 363 /* per-manager wake event flags; indexed by SoundWire manager instance (0-3) */ 364 bool acp7x_sdw_wake_event[ACP7X_SDW_MAX_MANAGER_COUNT]; 365 /* PDM controller index selected from ACPI acp-audio-ep-port; passed to machine driver */ 366 unsigned int pdm_sel; 367 bool is_sdw_dev; 368 unsigned int pci_rev; 369 u32 subsystem_vendor; 370 u32 subsystem_device; 371 int acp_sof_signed_firmware_image; 372 /* ACP7.F ASP carveout firmware load state */ 373 u64 asp_carveout_base; 374 u32 asp_carveout_size; 375 u32 asp_carveout_group_start; /* first ATU group index for carveout (from ASP) */ 376 u32 asp_carveout_group_count; /* number of consecutive ATU groups for carveout */ 377 /* 378 * Physical address and raw size of each validated DSP code binary 379 * within the carveout region (returned by ASP VALIDATE_IMAGE). 380 * Preserved across suspend/resume so that SHA DMA can reload DSP IRAM 381 * from the carveout without re-authenticating from disk. 382 */ 383 u64 fw_code_carveout_addr; 384 u32 fw_code_raw_size; 385 /* Real CPU physical address of the ASP MPASP mailbox payload page */ 386 phys_addr_t asp_mbox_buf_phys; 387 void *asp_mbox_buf; 388 /* 389 * SHA DMA completion for the carveout path. 390 * ACP_SHA_STAT (bit 15 of ACP_EXTERNAL_INTR_STAT) has no dedicated 391 * mask bit in ACP_EXTERNAL_INTR_CNTL - it is always enabled by default. 392 * SHA DMA is triggered exclusively during firmware loading, so no 393 * spurious ACP_SHA_STAT interrupts are expected outside that window. 394 * acp7x_irq_handler signals sha_dma_complete when ACP_SHA_STAT fires; 395 * configure_and_run_sha_dma() waits on it before polling 396 * ACP_SHA_DSP_FW_QUALIFIER to ensure ASP has validated the source. 397 */ 398 struct completion sha_dma_complete; 399 }; 400 401 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes); 402 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes); 403 404 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch); 405 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 406 unsigned int dest_addr, int dsp_data_size); 407 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 408 unsigned int start_addr, unsigned int dest_addr, 409 unsigned int image_length); 410 411 /* ACP device probe/remove */ 412 int amd_sof_acp_probe(struct snd_sof_dev *sdev); 413 void amd_sof_acp_remove(struct snd_sof_dev *sdev); 414 415 /* DSP Loader callbacks */ 416 int acp_sof_dsp_run(struct snd_sof_dev *sdev); 417 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev); 418 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev); 419 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type); 420 421 /* ACP7.B/7.F ASP carveout firmware load helper functions */ 422 int acp7x_query_asp_carveout(struct snd_sof_dev *sdev); 423 int acp7x_load_firmware_carveout(struct snd_sof_dev *sdev); 424 int acp7x_configure_carveout_pte(struct snd_sof_dev *sdev); 425 426 /* Block IO callbacks */ 427 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 428 u32 offset, void *src, size_t size); 429 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type, 430 u32 offset, void *dest, size_t size); 431 432 /* IPC callbacks */ 433 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context); 434 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps, 435 void *p, size_t sz); 436 int acp_set_stream_data_offset(struct snd_sof_dev *sdev, 437 struct snd_sof_pcm_stream *sps, 438 size_t posn_offset); 439 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev, 440 struct snd_sof_ipc_msg *msg); 441 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev); 442 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id); 443 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 444 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes); 445 446 /* ACP - DSP stream callbacks */ 447 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream); 448 int acp_dsp_stream_init(struct snd_sof_dev *sdev); 449 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag); 450 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream); 451 452 /* 453 * DSP PCM Operations. 454 */ 455 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 456 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream); 457 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream, 458 struct snd_pcm_hw_params *params, 459 struct snd_sof_platform_stream_params *platform_params); 460 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev, 461 struct snd_pcm_substream *substream); 462 463 extern const struct snd_sof_dsp_ops sof_acp_common_ops; 464 465 extern struct snd_sof_dsp_ops sof_renoir_ops; 466 int sof_renoir_ops_init(struct snd_sof_dev *sdev); 467 extern struct snd_sof_dsp_ops sof_vangogh_ops; 468 int sof_vangogh_ops_init(struct snd_sof_dev *sdev); 469 extern struct snd_sof_dsp_ops sof_rembrandt_ops; 470 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 471 extern struct snd_sof_dsp_ops sof_acp63_ops; 472 int sof_acp63_ops_init(struct snd_sof_dev *sdev); 473 474 extern struct snd_sof_dsp_ops sof_acp70_ops; 475 int sof_acp70_ops_init(struct snd_sof_dev *sdev); 476 477 extern struct snd_sof_dsp_ops sof_acp7x_ops; 478 int sof_acp7x_ops_init(struct snd_sof_dev *sdev); 479 480 int amd_sof_acp7x_probe(struct snd_sof_dev *sdev); 481 void amd_sof_acp7x_remove(struct snd_sof_dev *sdev); 482 int amd_sof_acp7x_suspend(struct snd_sof_dev *sdev, u32 target_state); 483 int amd_sof_acp7x_resume(struct snd_sof_dev *sdev); 484 int amd_sof_acp7x_suspend_runtime(struct snd_sof_dev *sdev); 485 int amd_sof_acp7x_resume_runtime(struct snd_sof_dev *sdev); 486 487 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); 488 /* Machine configuration */ 489 int snd_amd_acp_find_config(struct pci_dev *pci); 490 491 /* Trace */ 492 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab, 493 struct sof_ipc_dma_trace_params_ext *dtrace_params); 494 int acp_sof_trace_release(struct snd_sof_dev *sdev); 495 496 /* PM Callbacks */ 497 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state); 498 int amd_sof_acp_resume(struct snd_sof_dev *sdev); 499 500 void amd_sof_ipc_dump(struct snd_sof_dev *sdev); 501 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags); 502 503 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata) 504 { 505 const struct sof_dev_desc *desc = pdata->desc; 506 507 return desc->chip_info; 508 } 509 510 int acp_probes_register(struct snd_sof_dev *sdev); 511 void acp_probes_unregister(struct snd_sof_dev *sdev); 512 513 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; 514 extern const struct dmi_system_id acp_sof_quirk_table[]; 515 #endif 516