1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 Support for Intel Camera Imaging ISP subsystem.
4 Copyright (c) 2010 - 2015, Intel Corporation.
5
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/math.h>
10
11 #include "ia_css_yuv444_io.host.h"
12 #include "dma.h"
13 #ifndef IA_CSS_NO_DEBUG
14 #include "ia_css_debug.h"
15 #endif
16 #include "ia_css_isp_params.h"
17 #include "ia_css_frame.h"
18
ia_css_yuv444_io_config(const struct ia_css_binary * binary,const struct sh_css_binary_args * args)19 int ia_css_yuv444_io_config(const struct ia_css_binary *binary,
20 const struct sh_css_binary_args *args)
21 {
22 const struct ia_css_frame *in_frame = args->in_frame;
23 const struct ia_css_frame **out_frames = (const struct ia_css_frame **)
24 &args->out_frame;
25 const struct ia_css_frame_info *in_frame_info = ia_css_frame_get_info(in_frame);
26 const unsigned int ddr_elems_per_word =
27 DIV_ROUND_UP(HIVE_ISP_DDR_WORD_BITS, BITS_PER_TYPE(short));
28 unsigned int size_get = 0, size_put = 0;
29 unsigned int offset = 0;
30 int ret;
31
32 if (binary->info->mem_offsets.offsets.param) {
33 size_get = binary->info->mem_offsets.offsets.param->dmem.get.size;
34 offset = binary->info->mem_offsets.offsets.param->dmem.get.offset;
35 }
36
37 if (size_get) {
38 struct ia_css_common_io_config *to = (struct ia_css_common_io_config *)
39 &binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset];
40 struct dma_port_config config;
41 #ifndef IA_CSS_NO_DEBUG
42 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
43 "ia_css_yuv444_io_config() get part enter:\n");
44 #endif
45
46 ret = ia_css_dma_configure_from_info(&config, in_frame_info);
47 if (ret)
48 return ret;
49
50 // The base_address of the input frame will be set in the ISP
51 to->width = in_frame_info->res.width;
52 to->height = in_frame_info->res.height;
53 to->stride = config.stride;
54 to->ddr_elems_per_word = ddr_elems_per_word;
55 #ifndef IA_CSS_NO_DEBUG
56 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
57 "ia_css_yuv444_io_config() get part leave:\n");
58 #endif
59 }
60
61 if (binary->info->mem_offsets.offsets.param) {
62 size_put = binary->info->mem_offsets.offsets.param->dmem.put.size;
63 offset = binary->info->mem_offsets.offsets.param->dmem.put.offset;
64 }
65
66 if (size_put) {
67 struct ia_css_common_io_config *to = (struct ia_css_common_io_config *)
68 &binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset];
69 struct dma_port_config config;
70 #ifndef IA_CSS_NO_DEBUG
71 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
72 "ia_css_yuv444_io_config() put part enter:\n");
73 #endif
74
75 ret = ia_css_dma_configure_from_info(&config, &out_frames[0]->frame_info);
76 if (ret)
77 return ret;
78
79 to->base_address = out_frames[0]->data;
80 to->width = out_frames[0]->frame_info.res.width;
81 to->height = out_frames[0]->frame_info.res.height;
82 to->stride = config.stride;
83 to->ddr_elems_per_word = ddr_elems_per_word;
84
85 #ifndef IA_CSS_NO_DEBUG
86 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE,
87 "ia_css_yuv444_io_config() put part leave:\n");
88 #endif
89 }
90 return 0;
91 }
92