1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc.h"
28 #include "dc_bios_types.h"
29 #include "core_types.h"
30 #include "core_status.h"
31 #include "resource.h"
32 #include "dm_helpers.h"
33 #include "dce110_hwseq.h"
34 #include "dce110/dce110_timing_generator.h"
35 #include "dce/dce_hwseq.h"
36 #include "gpio_service_interface.h"
37
38 #include "dce110/dce110_compressor.h"
39
40 #include "bios/bios_parser_helper.h"
41 #include "timing_generator.h"
42 #include "mem_input.h"
43 #include "opp.h"
44 #include "ipp.h"
45 #include "transform.h"
46 #include "stream_encoder.h"
47 #include "link_encoder.h"
48 #include "link_enc_cfg.h"
49 #include "link_hwss.h"
50 #include "link.h"
51 #include "dccg.h"
52 #include "clock_source.h"
53 #include "clk_mgr.h"
54 #include "abm.h"
55 #include "audio.h"
56 #include "reg_helper.h"
57 #include "panel_cntl.h"
58 #include "dc_state_priv.h"
59 #include "dpcd_defs.h"
60 #include "dsc.h"
61 /* include DCE11 register header files */
62 #include "dce/dce_11_0_d.h"
63 #include "dce/dce_11_0_sh_mask.h"
64 #include "custom_float.h"
65
66 #include "atomfirmware.h"
67
68 #include "dcn10/dcn10_hwseq.h"
69
70 #define GAMMA_HW_POINTS_NUM 256
71
72 /*
73 * All values are in milliseconds;
74 * For eDP, after power-up/power/down,
75 * 300/500 msec max. delay from LCDVCC to black video generation
76 */
77 #define PANEL_POWER_UP_TIMEOUT 300
78 #define PANEL_POWER_DOWN_TIMEOUT 500
79 #define HPD_CHECK_INTERVAL 10
80 #define OLED_POST_T7_DELAY 100
81 #define OLED_PRE_T11_DELAY 150
82
83 #define CTX \
84 hws->ctx
85
86 #define DC_LOGGER \
87 ctx->logger
88 #define DC_LOGGER_INIT() \
89 struct dc_context *ctx = dc->ctx
90
91 #define REG(reg)\
92 hws->regs->reg
93
94 #undef FN
95 #define FN(reg_name, field_name) \
96 hws->shifts->field_name, hws->masks->field_name
97
98 struct dce110_hw_seq_reg_offsets {
99 uint32_t crtc;
100 };
101
102 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
103 {
104 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
105 },
106 {
107 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
108 },
109 {
110 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
111 },
112 {
113 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
114 }
115 };
116
117 #define HW_REG_BLND(reg, id)\
118 (reg + reg_offsets[id].blnd)
119
120 #define HW_REG_CRTC(reg, id)\
121 (reg + reg_offsets[id].crtc)
122
123 #define MAX_WATERMARK 0xFFFF
124 #define SAFE_NBP_MARK 0x7FFF
125
126 /*******************************************************************************
127 * Private definitions
128 ******************************************************************************/
129 /***************************PIPE_CONTROL***********************************/
dce110_init_pte(struct dc_context * ctx)130 static void dce110_init_pte(struct dc_context *ctx)
131 {
132 uint32_t addr;
133 uint32_t value = 0;
134 uint32_t chunk_int = 0;
135 uint32_t chunk_mul = 0;
136
137 addr = mmUNP_DVMM_PTE_CONTROL;
138 value = dm_read_reg(ctx, addr);
139
140 set_reg_field_value(
141 value,
142 0,
143 DVMM_PTE_CONTROL,
144 DVMM_USE_SINGLE_PTE);
145
146 set_reg_field_value(
147 value,
148 1,
149 DVMM_PTE_CONTROL,
150 DVMM_PTE_BUFFER_MODE0);
151
152 set_reg_field_value(
153 value,
154 1,
155 DVMM_PTE_CONTROL,
156 DVMM_PTE_BUFFER_MODE1);
157
158 dm_write_reg(ctx, addr, value);
159
160 addr = mmDVMM_PTE_REQ;
161 value = dm_read_reg(ctx, addr);
162
163 chunk_int = get_reg_field_value(
164 value,
165 DVMM_PTE_REQ,
166 HFLIP_PTEREQ_PER_CHUNK_INT);
167
168 chunk_mul = get_reg_field_value(
169 value,
170 DVMM_PTE_REQ,
171 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
172
173 if (chunk_int != 0x4 || chunk_mul != 0x4) {
174
175 set_reg_field_value(
176 value,
177 255,
178 DVMM_PTE_REQ,
179 MAX_PTEREQ_TO_ISSUE);
180
181 set_reg_field_value(
182 value,
183 4,
184 DVMM_PTE_REQ,
185 HFLIP_PTEREQ_PER_CHUNK_INT);
186
187 set_reg_field_value(
188 value,
189 4,
190 DVMM_PTE_REQ,
191 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
192
193 dm_write_reg(ctx, addr, value);
194 }
195 }
196 /**************************************************************************/
197
enable_display_pipe_clock_gating(struct dc_context * ctx,bool clock_gating)198 static void enable_display_pipe_clock_gating(
199 struct dc_context *ctx,
200 bool clock_gating)
201 {
202 /*TODO*/
203 }
204
dce110_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)205 static bool dce110_enable_display_power_gating(
206 struct dc *dc,
207 uint8_t controller_id,
208 struct dc_bios *dcb,
209 enum pipe_gating_control power_gating)
210 {
211 enum bp_result bp_result = BP_RESULT_OK;
212 enum bp_pipe_control_action cntl;
213 struct dc_context *ctx = dc->ctx;
214 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
215
216 if (power_gating == PIPE_GATING_CONTROL_INIT)
217 cntl = ASIC_PIPE_INIT;
218 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
219 cntl = ASIC_PIPE_ENABLE;
220 else
221 cntl = ASIC_PIPE_DISABLE;
222
223 if (controller_id == underlay_idx)
224 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
225
226 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
227
228 bp_result = dcb->funcs->enable_disp_power_gating(
229 dcb, controller_id + 1, cntl);
230
231 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
232 * by default when command table is called
233 *
234 * Bios parser accepts controller_id = 6 as indicative of
235 * underlay pipe in dce110. But we do not support more
236 * than 3.
237 */
238 if (controller_id < CONTROLLER_ID_MAX - 1)
239 dm_write_reg(ctx,
240 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
241 0);
242 }
243
244 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
245 dce110_init_pte(ctx);
246
247 if (bp_result == BP_RESULT_OK)
248 return true;
249 else
250 return false;
251 }
252
dce110_prescale_params(struct ipp_prescale_params * prescale_params,const struct dc_plane_state * plane_state)253 static void dce110_prescale_params(struct ipp_prescale_params *prescale_params,
254 const struct dc_plane_state *plane_state)
255 {
256 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
257
258 switch (plane_state->format) {
259 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
260 prescale_params->scale = 0x2082;
261 break;
262 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
263 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
264 prescale_params->scale = 0x2020;
265 break;
266 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
267 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
268 prescale_params->scale = 0x2008;
269 break;
270 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
271 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
272 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
273 prescale_params->scale = 0x2000;
274 break;
275 default:
276 ASSERT(false);
277 break;
278 }
279 }
280
281 static bool
dce110_set_input_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_plane_state * plane_state)282 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
283 const struct dc_plane_state *plane_state)
284 {
285 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
286 const struct dc_transfer_func *tf = NULL;
287 struct ipp_prescale_params prescale_params = { 0 };
288 bool result = true;
289
290 if (ipp == NULL)
291 return false;
292
293 tf = &plane_state->in_transfer_func;
294
295 dce110_prescale_params(&prescale_params, plane_state);
296 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
297
298 if (!plane_state->gamma_correction.is_identity &&
299 dce_use_lut(plane_state->format))
300 ipp->funcs->ipp_program_input_lut(ipp, &plane_state->gamma_correction);
301
302 if (tf->type == TF_TYPE_PREDEFINED) {
303 switch (tf->tf) {
304 case TRANSFER_FUNCTION_SRGB:
305 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
306 break;
307 case TRANSFER_FUNCTION_BT709:
308 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
309 break;
310 case TRANSFER_FUNCTION_LINEAR:
311 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
312 break;
313 case TRANSFER_FUNCTION_PQ:
314 default:
315 result = false;
316 break;
317 }
318 } else if (tf->type == TF_TYPE_BYPASS) {
319 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
320 } else {
321 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
322 result = false;
323 }
324
325 return result;
326 }
327
convert_to_custom_float(struct pwl_result_data * rgb_resulted,struct curve_points * arr_points,uint32_t hw_points_num)328 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
329 struct curve_points *arr_points,
330 uint32_t hw_points_num)
331 {
332 struct custom_float_format fmt;
333
334 struct pwl_result_data *rgb = rgb_resulted;
335
336 uint32_t i = 0;
337
338 fmt.exponenta_bits = 6;
339 fmt.mantissa_bits = 12;
340 fmt.sign = true;
341
342 if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
343 &arr_points[0].custom_float_x)) {
344 BREAK_TO_DEBUGGER();
345 return false;
346 }
347
348 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
349 &arr_points[0].custom_float_offset)) {
350 BREAK_TO_DEBUGGER();
351 return false;
352 }
353
354 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
355 &arr_points[0].custom_float_slope)) {
356 BREAK_TO_DEBUGGER();
357 return false;
358 }
359
360 fmt.mantissa_bits = 10;
361 fmt.sign = false;
362
363 if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
364 &arr_points[1].custom_float_x)) {
365 BREAK_TO_DEBUGGER();
366 return false;
367 }
368
369 if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
370 &arr_points[1].custom_float_y)) {
371 BREAK_TO_DEBUGGER();
372 return false;
373 }
374
375 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
376 &arr_points[1].custom_float_slope)) {
377 BREAK_TO_DEBUGGER();
378 return false;
379 }
380
381 fmt.mantissa_bits = 12;
382 fmt.sign = true;
383
384 while (i != hw_points_num) {
385 if (!convert_to_custom_float_format(rgb->red, &fmt,
386 &rgb->red_reg)) {
387 BREAK_TO_DEBUGGER();
388 return false;
389 }
390
391 if (!convert_to_custom_float_format(rgb->green, &fmt,
392 &rgb->green_reg)) {
393 BREAK_TO_DEBUGGER();
394 return false;
395 }
396
397 if (!convert_to_custom_float_format(rgb->blue, &fmt,
398 &rgb->blue_reg)) {
399 BREAK_TO_DEBUGGER();
400 return false;
401 }
402
403 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
404 &rgb->delta_red_reg)) {
405 BREAK_TO_DEBUGGER();
406 return false;
407 }
408
409 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
410 &rgb->delta_green_reg)) {
411 BREAK_TO_DEBUGGER();
412 return false;
413 }
414
415 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
416 &rgb->delta_blue_reg)) {
417 BREAK_TO_DEBUGGER();
418 return false;
419 }
420
421 ++rgb;
422 ++i;
423 }
424
425 return true;
426 }
427
428 #define MAX_LOW_POINT 25
429 #define NUMBER_REGIONS 16
430 #define NUMBER_SW_SEGMENTS 16
431
432 static bool
dce110_translate_regamma_to_hw_format(const struct dc_transfer_func * output_tf,struct pwl_params * regamma_params)433 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
434 struct pwl_params *regamma_params)
435 {
436 struct curve_points *arr_points;
437 struct pwl_result_data *rgb_resulted;
438 struct pwl_result_data *rgb;
439 struct pwl_result_data *rgb_plus_1;
440 struct fixed31_32 y_r;
441 struct fixed31_32 y_g;
442 struct fixed31_32 y_b;
443 struct fixed31_32 y1_min;
444 struct fixed31_32 y3_max;
445
446 int32_t region_start, region_end;
447 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
448
449 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
450 return false;
451
452 arr_points = regamma_params->arr_points;
453 rgb_resulted = regamma_params->rgb_resulted;
454 hw_points = 0;
455
456 memset(regamma_params, 0, sizeof(struct pwl_params));
457
458 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
459 /* 16 segments
460 * segments are from 2^-11 to 2^5
461 */
462 region_start = -11;
463 region_end = region_start + NUMBER_REGIONS;
464
465 for (i = 0; i < NUMBER_REGIONS; i++)
466 seg_distr[i] = 4;
467
468 } else {
469 /* 10 segments
470 * segment is from 2^-10 to 2^1
471 * We include an extra segment for range [2^0, 2^1). This is to
472 * ensure that colors with normalized values of 1 don't miss the
473 * LUT.
474 */
475 region_start = -10;
476 region_end = 1;
477
478 seg_distr[0] = 4;
479 seg_distr[1] = 4;
480 seg_distr[2] = 4;
481 seg_distr[3] = 4;
482 seg_distr[4] = 4;
483 seg_distr[5] = 4;
484 seg_distr[6] = 4;
485 seg_distr[7] = 4;
486 seg_distr[8] = 4;
487 seg_distr[9] = 4;
488 seg_distr[10] = 0;
489 seg_distr[11] = -1;
490 seg_distr[12] = -1;
491 seg_distr[13] = -1;
492 seg_distr[14] = -1;
493 seg_distr[15] = -1;
494 }
495
496 for (k = 0; k < 16; k++) {
497 if (seg_distr[k] != -1)
498 hw_points += (1 << seg_distr[k]);
499 }
500
501 j = 0;
502 for (k = 0; k < (region_end - region_start); k++) {
503 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
504 start_index = (region_start + k + MAX_LOW_POINT) *
505 NUMBER_SW_SEGMENTS;
506 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
507 i += increment) {
508 if (j == hw_points - 1)
509 break;
510 rgb_resulted[j].red = output_tf->tf_pts.red[i];
511 rgb_resulted[j].green = output_tf->tf_pts.green[i];
512 rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
513 j++;
514 }
515 }
516
517 /* last point */
518 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
519 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
520 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
521 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
522
523 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
524 dc_fixpt_from_int(region_start));
525 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
526 dc_fixpt_from_int(region_end));
527
528 y_r = rgb_resulted[0].red;
529 y_g = rgb_resulted[0].green;
530 y_b = rgb_resulted[0].blue;
531
532 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
533
534 arr_points[0].y = y1_min;
535 arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
536 arr_points[0].x);
537
538 y_r = rgb_resulted[hw_points - 1].red;
539 y_g = rgb_resulted[hw_points - 1].green;
540 y_b = rgb_resulted[hw_points - 1].blue;
541
542 /* see comment above, m_arrPoints[1].y should be the Y value for the
543 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
544 */
545 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
546
547 arr_points[1].y = y3_max;
548
549 arr_points[1].slope = dc_fixpt_zero;
550
551 if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
552 /* for PQ, we want to have a straight line from last HW X point,
553 * and the slope to be such that we hit 1.0 at 10000 nits.
554 */
555 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
556
557 arr_points[1].slope = dc_fixpt_div(
558 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
559 dc_fixpt_sub(end_value, arr_points[1].x));
560 }
561
562 regamma_params->hw_points_num = hw_points;
563
564 k = 0;
565 for (i = 1; i < 16; i++) {
566 if (seg_distr[k] != -1) {
567 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
568 regamma_params->arr_curve_points[i].offset =
569 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
570 }
571 k++;
572 }
573
574 if (seg_distr[k] != -1)
575 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
576
577 rgb = rgb_resulted;
578 rgb_plus_1 = rgb_resulted + 1;
579
580 i = 1;
581
582 while (i != hw_points + 1) {
583 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
584 rgb_plus_1->red = rgb->red;
585 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
586 rgb_plus_1->green = rgb->green;
587 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
588 rgb_plus_1->blue = rgb->blue;
589
590 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
591 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
592 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
593
594 ++rgb_plus_1;
595 ++rgb;
596 ++i;
597 }
598
599 convert_to_custom_float(rgb_resulted, arr_points, hw_points);
600
601 return true;
602 }
603
604 static bool
dce110_set_output_transfer_func(struct dc * dc,struct pipe_ctx * pipe_ctx,const struct dc_stream_state * stream)605 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
606 const struct dc_stream_state *stream)
607 {
608 struct transform *xfm = pipe_ctx->plane_res.xfm;
609
610 xfm->funcs->opp_power_on_regamma_lut(xfm, true);
611 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
612
613 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED &&
614 stream->out_transfer_func.tf == TRANSFER_FUNCTION_SRGB) {
615 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
616 } else if (dce110_translate_regamma_to_hw_format(&stream->out_transfer_func,
617 &xfm->regamma_params)) {
618 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
619 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
620 } else {
621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
622 }
623
624 xfm->funcs->opp_power_on_regamma_lut(xfm, false);
625
626 return true;
627 }
628
dce110_update_info_frame(struct pipe_ctx * pipe_ctx)629 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
630 {
631 bool is_hdmi_tmds;
632 bool is_dp;
633
634 ASSERT(pipe_ctx->stream);
635
636 if (pipe_ctx->stream_res.stream_enc == NULL)
637 return; /* this is not root pipe */
638
639 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
640 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
641
642 if (!is_hdmi_tmds && !is_dp)
643 return;
644
645 if (is_hdmi_tmds)
646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
647 pipe_ctx->stream_res.stream_enc,
648 &pipe_ctx->stream_res.encoder_info_frame);
649 else {
650 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num)
651 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num(
652 pipe_ctx->stream_res.stream_enc,
653 &pipe_ctx->stream_res.encoder_info_frame);
654
655 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
656 pipe_ctx->stream_res.stream_enc,
657 &pipe_ctx->stream_res.encoder_info_frame);
658 }
659 }
660
dce110_enable_stream(struct pipe_ctx * pipe_ctx)661 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
662 {
663 enum dc_lane_count lane_count =
664 pipe_ctx->stream->link->cur_link_settings.lane_count;
665 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
666 struct dc_link *link = pipe_ctx->stream->link;
667 const struct dc *dc = link->dc;
668 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
669 uint32_t active_total_with_borders;
670 uint32_t early_control = 0;
671 struct timing_generator *tg = pipe_ctx->stream_res.tg;
672
673 link_hwss->setup_stream_encoder(pipe_ctx);
674
675 dc->hwss.update_info_frame(pipe_ctx);
676
677 /* enable early control to avoid corruption on DP monitor*/
678 active_total_with_borders =
679 timing->h_addressable
680 + timing->h_border_left
681 + timing->h_border_right;
682
683 if (lane_count != 0)
684 early_control = active_total_with_borders % lane_count;
685
686 if (early_control == 0)
687 early_control = lane_count;
688
689 tg->funcs->set_early_control(tg, early_control);
690 }
691
link_transmitter_control(struct dc_bios * bios,struct bp_transmitter_control * cntl)692 static enum bp_result link_transmitter_control(
693 struct dc_bios *bios,
694 struct bp_transmitter_control *cntl)
695 {
696 enum bp_result result;
697
698 result = bios->funcs->transmitter_control(bios, cntl);
699
700 return result;
701 }
702
703 /*
704 * @brief
705 * eDP only.
706 */
dce110_edp_wait_for_hpd_ready(struct dc_link * link,bool power_up)707 void dce110_edp_wait_for_hpd_ready(
708 struct dc_link *link,
709 bool power_up)
710 {
711 struct dc_context *ctx = link->ctx;
712 struct graphics_object_id connector = link->link_enc->connector;
713 struct gpio *hpd;
714 bool edp_hpd_high = false;
715 uint32_t time_elapsed = 0;
716 uint32_t timeout = power_up ?
717 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
718
719 if (dal_graphics_object_id_get_connector_id(connector)
720 != CONNECTOR_ID_EDP) {
721 BREAK_TO_DEBUGGER();
722 return;
723 }
724
725 if (!power_up)
726 /*
727 * From KV, we will not HPD low after turning off VCC -
728 * instead, we will check the SW timer in power_up().
729 */
730 return;
731
732 /*
733 * When we power on/off the eDP panel,
734 * we need to wait until SENSE bit is high/low.
735 */
736
737 /* obtain HPD */
738 /* TODO what to do with this? */
739 hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
740
741 if (!hpd) {
742 BREAK_TO_DEBUGGER();
743 return;
744 }
745
746 if (link->panel_config.pps.extra_t3_ms > 0) {
747 int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
748
749 msleep(extra_t3_in_ms);
750 }
751
752 dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
753
754 /* wait until timeout or panel detected */
755
756 do {
757 uint32_t detected = 0;
758
759 dal_gpio_get_value(hpd, &detected);
760
761 if (!(detected ^ power_up)) {
762 edp_hpd_high = true;
763 break;
764 }
765
766 msleep(HPD_CHECK_INTERVAL);
767
768 time_elapsed += HPD_CHECK_INTERVAL;
769 } while (time_elapsed < timeout);
770
771 dal_gpio_close(hpd);
772
773 dal_gpio_destroy_irq(&hpd);
774
775 /* ensure that the panel is detected */
776 if (!edp_hpd_high)
777 DC_LOG_DC("%s: wait timed out!\n", __func__);
778 }
779
dce110_edp_power_control(struct dc_link * link,bool power_up)780 void dce110_edp_power_control(
781 struct dc_link *link,
782 bool power_up)
783 {
784 struct dc_context *ctx = link->ctx;
785 struct bp_transmitter_control cntl = { 0 };
786 enum bp_result bp_result;
787 uint8_t pwrseq_instance;
788
789
790 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
791 != CONNECTOR_ID_EDP) {
792 BREAK_TO_DEBUGGER();
793 return;
794 }
795
796 if (!link->panel_cntl)
797 return;
798 if (power_up !=
799 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
800
801 unsigned long long current_ts = dm_get_timestamp(ctx);
802 unsigned long long time_since_edp_poweroff_ms =
803 div64_u64(dm_get_elapse_time_in_ns(
804 ctx,
805 current_ts,
806 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
807 unsigned long long time_since_edp_poweron_ms =
808 div64_u64(dm_get_elapse_time_in_ns(
809 ctx,
810 current_ts,
811 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000);
812 DC_LOG_HW_RESUME_S3(
813 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
814 __func__,
815 power_up,
816 current_ts,
817 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
818 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link),
819 time_since_edp_poweroff_ms,
820 time_since_edp_poweron_ms);
821
822 /* Send VBIOS command to prompt eDP panel power */
823 if (power_up) {
824 /* edp requires a min of 500ms from LCDVDD off to on */
825 unsigned long long remaining_min_edp_poweroff_time_ms = 500;
826
827 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
828 if (link->local_sink != NULL)
829 remaining_min_edp_poweroff_time_ms +=
830 link->panel_config.pps.extra_t12_ms;
831
832 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
833 if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
834 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
835 remaining_min_edp_poweroff_time_ms =
836 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
837 else
838 remaining_min_edp_poweroff_time_ms = 0;
839 }
840
841 if (remaining_min_edp_poweroff_time_ms) {
842 DC_LOG_HW_RESUME_S3(
843 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
844 __func__, remaining_min_edp_poweroff_time_ms);
845 msleep(remaining_min_edp_poweroff_time_ms);
846 DC_LOG_HW_RESUME_S3(
847 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
848 __func__, remaining_min_edp_poweroff_time_ms);
849 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
850 __func__, remaining_min_edp_poweroff_time_ms);
851 } else {
852 DC_LOG_HW_RESUME_S3(
853 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
854 __func__, remaining_min_edp_poweroff_time_ms);
855 }
856 }
857
858 DC_LOG_HW_RESUME_S3(
859 "%s: BEGIN: Panel Power action: %s\n",
860 __func__, (power_up ? "On":"Off"));
861
862 cntl.action = power_up ?
863 TRANSMITTER_CONTROL_POWER_ON :
864 TRANSMITTER_CONTROL_POWER_OFF;
865 cntl.transmitter = link->link_enc->transmitter;
866 cntl.connector_obj_id = link->link_enc->connector;
867 cntl.coherent = false;
868 cntl.lanes_number = LANE_COUNT_FOUR;
869 cntl.hpd_sel = link->link_enc->hpd_source;
870 pwrseq_instance = link->panel_cntl->pwrseq_inst;
871
872 if (ctx->dc->ctx->dmub_srv &&
873 ctx->dc->debug.dmub_command_table) {
874
875 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) {
876 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
877 LVTMA_CONTROL_POWER_ON,
878 pwrseq_instance, link->link_powered_externally);
879 } else {
880 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
881 LVTMA_CONTROL_POWER_OFF,
882 pwrseq_instance, link->link_powered_externally);
883 }
884 }
885
886 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
887
888 DC_LOG_HW_RESUME_S3(
889 "%s: END: Panel Power action: %s bp_result=%u\n",
890 __func__, (power_up ? "On":"Off"),
891 bp_result);
892
893 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up);
894
895 DC_LOG_HW_RESUME_S3(
896 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
897 __func__,
898 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link),
899 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link));
900
901 if (bp_result != BP_RESULT_OK)
902 DC_LOG_ERROR(
903 "%s: Panel Power bp_result: %d\n",
904 __func__, bp_result);
905 } else {
906 DC_LOG_HW_RESUME_S3(
907 "%s: Skipping Panel Power action: %s\n",
908 __func__, (power_up ? "On":"Off"));
909 }
910 }
911
dce110_edp_wait_for_T12(struct dc_link * link)912 void dce110_edp_wait_for_T12(
913 struct dc_link *link)
914 {
915 struct dc_context *ctx = link->ctx;
916
917 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
918 != CONNECTOR_ID_EDP) {
919 BREAK_TO_DEBUGGER();
920 return;
921 }
922
923 if (!link->panel_cntl)
924 return;
925
926 if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
927 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) {
928 unsigned int t12_duration = 500; // Default T12 as per spec
929 unsigned long long current_ts = dm_get_timestamp(ctx);
930 unsigned long long time_since_edp_poweroff_ms =
931 div64_u64(dm_get_elapse_time_in_ns(
932 ctx,
933 current_ts,
934 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
935
936 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
937
938 if (time_since_edp_poweroff_ms < t12_duration)
939 msleep(t12_duration - time_since_edp_poweroff_ms);
940 }
941 }
942 /*todo: cloned in stream enc, fix*/
943 /*
944 * @brief
945 * eDP only. Control the backlight of the eDP panel
946 */
dce110_edp_backlight_control(struct dc_link * link,bool enable)947 void dce110_edp_backlight_control(
948 struct dc_link *link,
949 bool enable)
950 {
951 struct dc_context *ctx = link->ctx;
952 struct bp_transmitter_control cntl = { 0 };
953 uint8_t pwrseq_instance = 0;
954 unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;
955 unsigned int post_T7_delay = OLED_POST_T7_DELAY;
956
957 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
958 != CONNECTOR_ID_EDP) {
959 BREAK_TO_DEBUGGER();
960 return;
961 }
962
963 if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled ||
964 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
965 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
966 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
967
968 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
969 DC_LOG_HW_RESUME_S3(
970 "%s: panel already powered up/off. Do nothing.\n",
971 __func__);
972 return;
973 }
974 }
975
976 /* Send VBIOS command to control eDP panel backlight */
977
978 DC_LOG_HW_RESUME_S3(
979 "%s: backlight action: %s\n",
980 __func__, (enable ? "On":"Off"));
981
982 cntl.action = enable ?
983 TRANSMITTER_CONTROL_BACKLIGHT_ON :
984 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
985
986 /*cntl.engine_id = ctx->engine;*/
987 cntl.transmitter = link->link_enc->transmitter;
988 cntl.connector_obj_id = link->link_enc->connector;
989 /*todo: unhardcode*/
990 cntl.lanes_number = LANE_COUNT_FOUR;
991 cntl.hpd_sel = link->link_enc->hpd_source;
992 cntl.signal = SIGNAL_TYPE_EDP;
993
994 /* For eDP, the following delays might need to be considered
995 * after link training completed:
996 * idle period - min. accounts for required BS-Idle pattern,
997 * max. allows for source frame synchronization);
998 * 50 msec max. delay from valid video data from source
999 * to video on dislpay or backlight enable.
1000 *
1001 * Disable the delay for now.
1002 * Enable it in the future if necessary.
1003 */
1004 /* dc_service_sleep_in_milliseconds(50); */
1005 /*edp 1.2*/
1006 if (link->panel_cntl)
1007 pwrseq_instance = link->panel_cntl->pwrseq_inst;
1008
1009 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
1010 if (!link->dc->config.edp_no_power_sequencing)
1011 /*
1012 * Sometimes, DP receiver chip power-controlled externally by an
1013 * Embedded Controller could be treated and used as eDP,
1014 * if it drives mobile display. In this case,
1015 * we shouldn't be doing power-sequencing, hence we can skip
1016 * waiting for T7-ready.
1017 */
1018 ctx->dc->link_srv->edp_receiver_ready_T7(link);
1019 else
1020 DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
1021 }
1022
1023 /* Setting link_powered_externally will bypass delays in the backlight
1024 * as they are not required if the link is being powered by a different
1025 * source.
1026 */
1027 if (ctx->dc->ctx->dmub_srv &&
1028 ctx->dc->debug.dmub_command_table) {
1029 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1030 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1031 LVTMA_CONTROL_LCD_BLON,
1032 pwrseq_instance, link->link_powered_externally);
1033 else
1034 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1035 LVTMA_CONTROL_LCD_BLOFF,
1036 pwrseq_instance, link->link_powered_externally);
1037 }
1038
1039 link_transmitter_control(ctx->dc_bios, &cntl);
1040
1041 if (enable && link->dpcd_sink_ext_caps.bits.oled &&
1042 !link->dc->config.edp_no_power_sequencing &&
1043 !link->local_sink->edid_caps.panel_patch.oled_optimize_display_on) {
1044 post_T7_delay += link->panel_config.pps.extra_post_t7_ms;
1045 msleep(post_T7_delay);
1046 }
1047
1048 if (link->dpcd_sink_ext_caps.bits.oled ||
1049 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1050 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1051 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable);
1052
1053 /*edp 1.2*/
1054 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
1055 if (!link->dc->config.edp_no_power_sequencing)
1056 /*
1057 * Sometimes, DP receiver chip power-controlled externally by an
1058 * Embedded Controller could be treated and used as eDP,
1059 * if it drives mobile display. In this case,
1060 * we shouldn't be doing power-sequencing, hence we can skip
1061 * waiting for T9-ready.
1062 */
1063 ctx->dc->link_srv->edp_add_delay_for_T9(link);
1064 else
1065 DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
1066 }
1067
1068 if (!enable && link->dpcd_sink_ext_caps.bits.oled) {
1069 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;
1070 msleep(pre_T11_delay);
1071 }
1072 }
1073
dce110_enable_audio_stream(struct pipe_ctx * pipe_ctx)1074 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1075 {
1076 /* notify audio driver for audio modes of monitor */
1077 struct dc *dc;
1078 struct clk_mgr *clk_mgr;
1079 unsigned int i, num_audio = 1;
1080 const struct link_hwss *link_hwss;
1081
1082 if (!pipe_ctx->stream)
1083 return;
1084
1085 dc = pipe_ctx->stream->ctx->dc;
1086 clk_mgr = dc->clk_mgr;
1087 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1088
1089 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1090 return;
1091
1092 if (pipe_ctx->stream_res.audio) {
1093 for (i = 0; i < MAX_PIPES; i++) {
1094 /*current_state not updated yet*/
1095 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1096 num_audio++;
1097 }
1098
1099 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1100
1101 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1102 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1103 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1104
1105 link_hwss->enable_audio_packet(pipe_ctx);
1106
1107 if (pipe_ctx->stream_res.audio)
1108 pipe_ctx->stream_res.audio->enabled = true;
1109 }
1110 }
1111
dce110_disable_audio_stream(struct pipe_ctx * pipe_ctx)1112 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1113 {
1114 struct dc *dc;
1115 struct clk_mgr *clk_mgr;
1116 const struct link_hwss *link_hwss;
1117
1118 if (!pipe_ctx || !pipe_ctx->stream)
1119 return;
1120
1121 dc = pipe_ctx->stream->ctx->dc;
1122 clk_mgr = dc->clk_mgr;
1123 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res);
1124
1125 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1126 return;
1127
1128 link_hwss->disable_audio_packet(pipe_ctx);
1129
1130 if (pipe_ctx->stream_res.audio) {
1131 pipe_ctx->stream_res.audio->enabled = false;
1132
1133 if (clk_mgr->funcs->enable_pme_wa)
1134 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1135 clk_mgr->funcs->enable_pme_wa(clk_mgr);
1136
1137 /* TODO: notify audio driver for if audio modes list changed
1138 * add audio mode list change flag */
1139 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1140 * stream->stream_engine_id);
1141 */
1142 }
1143 }
1144
dce110_disable_stream(struct pipe_ctx * pipe_ctx)1145 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1146 {
1147 struct dc_stream_state *stream = pipe_ctx->stream;
1148 struct dc_link *link = stream->link;
1149 struct dc *dc = pipe_ctx->stream->ctx->dc;
1150 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1151 struct dccg *dccg = dc->res_pool->dccg;
1152 struct timing_generator *tg = pipe_ctx->stream_res.tg;
1153 struct dtbclk_dto_params dto_params = {0};
1154 int dp_hpo_inst;
1155 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
1156 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
1157
1158 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1159 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1160 pipe_ctx->stream_res.stream_enc);
1161 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1162 pipe_ctx->stream_res.stream_enc);
1163 }
1164
1165 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1166 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets(
1167 pipe_ctx->stream_res.hpo_dp_stream_enc);
1168 } else if (dc_is_dp_signal(pipe_ctx->stream->signal))
1169 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1170 pipe_ctx->stream_res.stream_enc);
1171
1172 dc->hwss.disable_audio_stream(pipe_ctx);
1173
1174 link_hwss->reset_stream_encoder(pipe_ctx);
1175
1176 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {
1177 dto_params.otg_inst = tg->inst;
1178 dto_params.timing = &pipe_ctx->stream->timing;
1179 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
1180 if (dccg) {
1181 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
1182 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
1183 if (dccg && dccg->funcs->set_dtbclk_dto)
1184 dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
1185 }
1186 } else if (dccg && dccg->funcs->disable_symclk_se) {
1187 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
1188 link_enc->transmitter - TRANSMITTER_UNIPHY_A);
1189 }
1190 }
1191
dce110_unblank_stream(struct pipe_ctx * pipe_ctx,struct dc_link_settings * link_settings)1192 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1193 struct dc_link_settings *link_settings)
1194 {
1195 struct encoder_unblank_param params = { { 0 } };
1196 struct dc_stream_state *stream = pipe_ctx->stream;
1197 struct dc_link *link = stream->link;
1198 struct dce_hwseq *hws = link->dc->hwseq;
1199
1200 /* only 3 items below are used by unblank */
1201 params.timing = pipe_ctx->stream->timing;
1202 params.link_settings.link_rate = link_settings->link_rate;
1203
1204 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1205 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms);
1206
1207 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1208 hws->funcs.edp_backlight_control(link, true);
1209 }
1210 }
1211
dce110_blank_stream(struct pipe_ctx * pipe_ctx)1212 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1213 {
1214 struct dc_stream_state *stream = pipe_ctx->stream;
1215 struct dc_link *link = stream->link;
1216 struct dce_hwseq *hws = link->dc->hwseq;
1217
1218 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1219 if (!link->skip_implict_edp_power_control)
1220 hws->funcs.edp_backlight_control(link, false);
1221 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1222 }
1223
1224 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1225 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */
1226 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank(
1227 pipe_ctx->stream_res.hpo_dp_stream_enc);
1228 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1229 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc);
1230
1231 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1232 /*
1233 * After output is idle pattern some sinks need time to recognize the stream
1234 * has changed or they enter protection state and hang.
1235 */
1236 msleep(60);
1237 }
1238 }
1239
1240 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
1241 !link->dc->config.edp_no_power_sequencing) {
1242 /*
1243 * Sometimes, DP receiver chip power-controlled externally by an
1244 * Embedded Controller could be treated and used as eDP,
1245 * if it drives mobile display. In this case,
1246 * we shouldn't be doing power-sequencing, hence we can skip
1247 * waiting for T9-ready.
1248 */
1249 link->dc->link_srv->edp_receiver_ready_T9(link);
1250 }
1251
1252 }
1253
1254
dce110_set_avmute(struct pipe_ctx * pipe_ctx,bool enable)1255 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1256 {
1257 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1258 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1259 }
1260
translate_to_dto_source(enum controller_id crtc_id)1261 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1262 {
1263 switch (crtc_id) {
1264 case CONTROLLER_ID_D0:
1265 return DTO_SOURCE_ID0;
1266 case CONTROLLER_ID_D1:
1267 return DTO_SOURCE_ID1;
1268 case CONTROLLER_ID_D2:
1269 return DTO_SOURCE_ID2;
1270 case CONTROLLER_ID_D3:
1271 return DTO_SOURCE_ID3;
1272 case CONTROLLER_ID_D4:
1273 return DTO_SOURCE_ID4;
1274 case CONTROLLER_ID_D5:
1275 return DTO_SOURCE_ID5;
1276 default:
1277 return DTO_SOURCE_UNKNOWN;
1278 }
1279 }
1280
populate_audio_dp_link_info(const struct pipe_ctx * pipe_ctx,struct audio_dp_link_info * dp_link_info)1281 static void populate_audio_dp_link_info(
1282 const struct pipe_ctx *pipe_ctx,
1283 struct audio_dp_link_info *dp_link_info)
1284 {
1285 const struct dc_stream_state *stream = pipe_ctx->stream;
1286 const struct dc_link *link = stream->link;
1287 struct fixed31_32 link_bw_kbps;
1288
1289 dp_link_info->encoding = link->dc->link_srv->dp_get_encoding_format(
1290 &pipe_ctx->link_config.dp_link_settings);
1291 dp_link_info->is_mst = (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST);
1292 dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count;
1293 dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate;
1294
1295 link_bw_kbps = dc_fixpt_from_int(dc_link_bandwidth_kbps(link,
1296 &pipe_ctx->link_config.dp_link_settings));
1297
1298 /* For audio stream calculations, the video stream should not include FEC or SSC
1299 * in order to get the most pessimistic values.
1300 */
1301 if (dp_link_info->encoding == DP_8b_10b_ENCODING &&
1302 link->dc->link_srv->dp_is_fec_supported(link)) {
1303 link_bw_kbps = dc_fixpt_mul(link_bw_kbps,
1304 dc_fixpt_from_fraction(100, DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100));
1305 } else if (dp_link_info->encoding == DP_128b_132b_ENCODING) {
1306 link_bw_kbps = dc_fixpt_mul(link_bw_kbps,
1307 dc_fixpt_from_fraction(10000, 9975)); /* 99.75% SSC overhead*/
1308 }
1309
1310 dp_link_info->link_bandwidth_kbps = dc_fixpt_floor(link_bw_kbps);
1311
1312 /* Calculates hblank_min_symbol_width for 128b/132b
1313 * Corresponding HBLANK_MIN_SYMBOL_WIDTH register is calculated as:
1314 * floor(h_blank * bits_per_pixel / 128)
1315 */
1316 if (dp_link_info->encoding == DP_128b_132b_ENCODING) {
1317 struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing;
1318
1319 uint32_t h_active = crtc_timing->h_addressable + crtc_timing->h_border_left
1320 + crtc_timing->h_border_right;
1321 uint32_t h_blank = crtc_timing->h_total - h_active;
1322
1323 uint32_t bpp;
1324
1325 if (crtc_timing->flags.DSC) {
1326 bpp = crtc_timing->dsc_cfg.bits_per_pixel;
1327 } else {
1328 /* When the timing is using DSC, dsc_cfg.bits_per_pixel is in 16th bits.
1329 * The bpp in this path is scaled to 16th bits so the final calculation
1330 * is correct for both cases.
1331 */
1332 bpp = 16;
1333 switch (crtc_timing->display_color_depth) {
1334 case COLOR_DEPTH_666:
1335 bpp *= 18;
1336 break;
1337 case COLOR_DEPTH_888:
1338 bpp *= 24;
1339 break;
1340 case COLOR_DEPTH_101010:
1341 bpp *= 30;
1342 break;
1343 case COLOR_DEPTH_121212:
1344 bpp *= 36;
1345 break;
1346 default:
1347 bpp = 0;
1348 break;
1349 }
1350
1351 switch (crtc_timing->pixel_encoding) {
1352 case PIXEL_ENCODING_YCBCR422:
1353 bpp = bpp * 2 / 3;
1354 break;
1355 case PIXEL_ENCODING_YCBCR420:
1356 bpp /= 2;
1357 break;
1358 default:
1359 break;
1360 }
1361 }
1362
1363 /* Min symbol width = floor(h_blank * (bpp/16) / 128) */
1364 dp_link_info->hblank_min_symbol_width = dc_fixpt_floor(
1365 dc_fixpt_div(dc_fixpt_from_int(h_blank * bpp),
1366 dc_fixpt_from_int(128 / 16)));
1367
1368 } else {
1369 dp_link_info->hblank_min_symbol_width = 0;
1370 }
1371 }
1372
build_audio_output(struct dc_state * state,const struct pipe_ctx * pipe_ctx,struct audio_output * audio_output)1373 static void build_audio_output(
1374 struct dc_state *state,
1375 const struct pipe_ctx *pipe_ctx,
1376 struct audio_output *audio_output)
1377 {
1378 const struct dc_stream_state *stream = pipe_ctx->stream;
1379 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1380
1381 audio_output->signal = pipe_ctx->stream->signal;
1382
1383 /* audio_crtc_info */
1384
1385 audio_output->crtc_info.h_total =
1386 stream->timing.h_total;
1387
1388 /*
1389 * Audio packets are sent during actual CRTC blank physical signal, we
1390 * need to specify actual active signal portion
1391 */
1392 audio_output->crtc_info.h_active =
1393 stream->timing.h_addressable
1394 + stream->timing.h_border_left
1395 + stream->timing.h_border_right;
1396
1397 audio_output->crtc_info.v_active =
1398 stream->timing.v_addressable
1399 + stream->timing.v_border_top
1400 + stream->timing.v_border_bottom;
1401
1402 audio_output->crtc_info.pixel_repetition = 1;
1403
1404 audio_output->crtc_info.interlaced =
1405 stream->timing.flags.INTERLACE;
1406
1407 audio_output->crtc_info.refresh_rate =
1408 (stream->timing.pix_clk_100hz*100)/
1409 (stream->timing.h_total*stream->timing.v_total);
1410
1411 audio_output->crtc_info.color_depth =
1412 stream->timing.display_color_depth;
1413
1414 audio_output->crtc_info.requested_pixel_clock_100Hz =
1415 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1416
1417 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1418 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1419
1420 audio_output->crtc_info.pixel_encoding =
1421 stream->timing.pixel_encoding;
1422
1423 audio_output->crtc_info.dsc_bits_per_pixel =
1424 stream->timing.dsc_cfg.bits_per_pixel;
1425
1426 audio_output->crtc_info.dsc_num_slices =
1427 stream->timing.dsc_cfg.num_slices_h;
1428
1429 /*for HDMI, audio ACR is with deep color ratio factor*/
1430 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1431 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1432 (stream->timing.pix_clk_100hz)) {
1433 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1434 audio_output->crtc_info.requested_pixel_clock_100Hz =
1435 audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1436 audio_output->crtc_info.calculated_pixel_clock_100Hz =
1437 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1438
1439 }
1440 }
1441
1442 if (state->clk_mgr &&
1443 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1444 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1445 audio_output->pll_info.audio_dto_source_clock_in_khz =
1446 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1447 state->clk_mgr);
1448 }
1449
1450 audio_output->pll_info.feed_back_divider =
1451 pipe_ctx->pll_settings.feedback_divider;
1452
1453 audio_output->pll_info.dto_source =
1454 translate_to_dto_source(
1455 pipe_ctx->stream_res.tg->inst + 1);
1456
1457 /* TODO hard code to enable for now. Need get from stream */
1458 audio_output->pll_info.ss_enabled = true;
1459
1460 audio_output->pll_info.ss_percentage =
1461 pipe_ctx->pll_settings.ss_percentage;
1462
1463 if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1464 populate_audio_dp_link_info(pipe_ctx, &audio_output->dp_link_info);
1465 }
1466 }
1467
program_scaler(const struct dc * dc,const struct pipe_ctx * pipe_ctx)1468 static void program_scaler(const struct dc *dc,
1469 const struct pipe_ctx *pipe_ctx)
1470 {
1471 struct tg_color color = {0};
1472
1473 /* TOFPGA */
1474 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1475 return;
1476
1477 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1478 get_surface_visual_confirm_color(pipe_ctx, &color);
1479 else
1480 color_space_to_black_color(dc,
1481 pipe_ctx->stream->output_color_space,
1482 &color);
1483
1484 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1485 pipe_ctx->plane_res.xfm,
1486 pipe_ctx->plane_res.scl_data.lb_params.depth,
1487 &pipe_ctx->stream->bit_depth_params);
1488
1489 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1490 /*
1491 * The way 420 is packed, 2 channels carry Y component, 1 channel
1492 * alternate between Cb and Cr, so both channels need the pixel
1493 * value for Y
1494 */
1495 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1496 color.color_r_cr = color.color_g_y;
1497
1498 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1499 pipe_ctx->stream_res.tg,
1500 &color);
1501 }
1502
1503 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1504 &pipe_ctx->plane_res.scl_data);
1505 }
1506
dce110_enable_stream_timing(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc)1507 static enum dc_status dce110_enable_stream_timing(
1508 struct pipe_ctx *pipe_ctx,
1509 struct dc_state *context,
1510 struct dc *dc)
1511 {
1512 struct dc_stream_state *stream = pipe_ctx->stream;
1513 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1514 pipe_ctx[pipe_ctx->pipe_idx];
1515 struct tg_color black_color = {0};
1516
1517 if (!pipe_ctx_old->stream) {
1518
1519 /* program blank color */
1520 color_space_to_black_color(dc,
1521 stream->output_color_space, &black_color);
1522 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1523 pipe_ctx->stream_res.tg,
1524 &black_color);
1525
1526 /*
1527 * Must blank CRTC after disabling power gating and before any
1528 * programming, otherwise CRTC will be hung in bad state
1529 */
1530 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1531
1532 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1533 pipe_ctx->clock_source,
1534 &pipe_ctx->stream_res.pix_clk_params,
1535 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings),
1536 &pipe_ctx->pll_settings)) {
1537 BREAK_TO_DEBUGGER();
1538 return DC_ERROR_UNEXPECTED;
1539 }
1540
1541 if (dc_is_hdmi_tmds_signal(stream->signal)) {
1542 stream->link->phy_state.symclk_ref_cnts.otg = 1;
1543 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF)
1544 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
1545 else
1546 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
1547 }
1548
1549 pipe_ctx->stream_res.tg->funcs->program_timing(
1550 pipe_ctx->stream_res.tg,
1551 &stream->timing,
1552 0,
1553 0,
1554 0,
1555 0,
1556 0,
1557 pipe_ctx->stream->signal,
1558 true);
1559 }
1560
1561 if (!pipe_ctx_old->stream) {
1562 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1563 pipe_ctx->stream_res.tg)) {
1564 BREAK_TO_DEBUGGER();
1565 return DC_ERROR_UNEXPECTED;
1566 }
1567 }
1568
1569 return DC_OK;
1570 }
1571
dce110_apply_single_controller_ctx_to_hw(struct pipe_ctx * pipe_ctx,struct dc_state * context,struct dc * dc)1572 enum dc_status dce110_apply_single_controller_ctx_to_hw(
1573 struct pipe_ctx *pipe_ctx,
1574 struct dc_state *context,
1575 struct dc *dc)
1576 {
1577 struct dc_stream_state *stream = pipe_ctx->stream;
1578 struct dc_link *link = stream->link;
1579 struct drr_params params = {0};
1580 unsigned int event_triggers = 0;
1581 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1582 struct dce_hwseq *hws = dc->hwseq;
1583 const struct link_hwss *link_hwss = get_link_hwss(
1584 link, &pipe_ctx->link_res);
1585
1586
1587 if (hws->funcs.disable_stream_gating) {
1588 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1589 }
1590
1591 if (pipe_ctx->stream_res.audio != NULL) {
1592 struct audio_output audio_output = {0};
1593
1594 build_audio_output(context, pipe_ctx, &audio_output);
1595
1596 link_hwss->setup_audio_output(pipe_ctx, &audio_output,
1597 pipe_ctx->stream_res.audio->inst);
1598
1599 pipe_ctx->stream_res.audio->funcs->az_configure(
1600 pipe_ctx->stream_res.audio,
1601 pipe_ctx->stream->signal,
1602 &audio_output.crtc_info,
1603 &pipe_ctx->stream->audio_info,
1604 &audio_output.dp_link_info);
1605
1606 if (dc->config.disable_hbr_audio_dp2)
1607 if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio &&
1608 dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))
1609 pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio(pipe_ctx->stream_res.audio);
1610 }
1611
1612 /* make sure no pipes syncd to the pipe being enabled */
1613 if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic)
1614 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx);
1615
1616 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1617 pipe_ctx->stream_res.opp,
1618 &stream->bit_depth_params,
1619 &stream->clamping);
1620
1621 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1622 pipe_ctx->stream_res.opp,
1623 COLOR_SPACE_YCBCR601,
1624 stream->timing.display_color_depth,
1625 stream->signal);
1626
1627 while (odm_pipe) {
1628 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1629 odm_pipe->stream_res.opp,
1630 COLOR_SPACE_YCBCR601,
1631 stream->timing.display_color_depth,
1632 stream->signal);
1633
1634 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1635 odm_pipe->stream_res.opp,
1636 &stream->bit_depth_params,
1637 &stream->clamping);
1638 odm_pipe = odm_pipe->next_odm_pipe;
1639 }
1640
1641 /* DCN3.1 FPGA Workaround
1642 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1643 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1644 * function core_link_enable_stream
1645 */
1646 if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)))
1647 /* */
1648 /* Do not touch stream timing on seamless boot optimization. */
1649 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1650 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1651
1652 if (hws->funcs.setup_vupdate_interrupt)
1653 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1654
1655 params.vertical_total_min = stream->adjust.v_total_min;
1656 params.vertical_total_max = stream->adjust.v_total_max;
1657 if (pipe_ctx->stream_res.tg->funcs->set_drr)
1658 pipe_ctx->stream_res.tg->funcs->set_drr(
1659 pipe_ctx->stream_res.tg, ¶ms);
1660
1661 // DRR should set trigger event to monitor surface update event
1662 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1663 event_triggers = 0x80;
1664 /* Event triggers and num frames initialized for DRR, but can be
1665 * later updated for PSR use. Note DRR trigger events are generated
1666 * regardless of whether num frames met.
1667 */
1668 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1669 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1670 pipe_ctx->stream_res.tg, event_triggers, 2);
1671
1672 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1673 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1674 pipe_ctx->stream_res.stream_enc,
1675 pipe_ctx->stream_res.tg->inst);
1676
1677 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1678 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG);
1679
1680 if (!stream->dpms_off)
1681 dc->link_srv->set_dpms_on(context, pipe_ctx);
1682
1683 /* DCN3.1 FPGA Workaround
1684 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1685 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1686 * function core_link_enable_stream
1687 */
1688 if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
1689 if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1690 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1691 }
1692
1693 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
1694
1695 /* Phantom and main stream share the same link (because the stream
1696 * is constructed with the same sink). Make sure not to override
1697 * and link programming on the main.
1698 */
1699 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) {
1700 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1701 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false;
1702 }
1703 return DC_OK;
1704 }
1705
1706 /******************************************************************************/
1707
power_down_encoders(struct dc * dc)1708 static void power_down_encoders(struct dc *dc)
1709 {
1710 int i;
1711
1712 for (i = 0; i < dc->link_count; i++) {
1713 enum signal_type signal = dc->links[i]->connector_signal;
1714
1715 dc->link_srv->blank_dp_stream(dc->links[i], false);
1716
1717 if (signal != SIGNAL_TYPE_EDP)
1718 signal = SIGNAL_TYPE_NONE;
1719
1720 if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY)
1721 dc->links[i]->link_enc->funcs->disable_output(
1722 dc->links[i]->link_enc, signal);
1723
1724 dc->links[i]->link_status.link_active = false;
1725 memset(&dc->links[i]->cur_link_settings, 0,
1726 sizeof(dc->links[i]->cur_link_settings));
1727 }
1728 }
1729
power_down_controllers(struct dc * dc)1730 static void power_down_controllers(struct dc *dc)
1731 {
1732 int i;
1733
1734 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1735 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1736 dc->res_pool->timing_generators[i]);
1737 }
1738 }
1739
power_down_clock_sources(struct dc * dc)1740 static void power_down_clock_sources(struct dc *dc)
1741 {
1742 int i;
1743
1744 if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1745 dc->res_pool->dp_clock_source) == false)
1746 dm_error("Failed to power down pll! (dp clk src)\n");
1747
1748 for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1749 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1750 dc->res_pool->clock_sources[i]) == false)
1751 dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1752 }
1753 }
1754
power_down_all_hw_blocks(struct dc * dc)1755 static void power_down_all_hw_blocks(struct dc *dc)
1756 {
1757 power_down_encoders(dc);
1758
1759 power_down_controllers(dc);
1760
1761 power_down_clock_sources(dc);
1762
1763 if (dc->fbc_compressor)
1764 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1765 }
1766
disable_vga_and_power_gate_all_controllers(struct dc * dc)1767 static void disable_vga_and_power_gate_all_controllers(
1768 struct dc *dc)
1769 {
1770 int i;
1771 struct timing_generator *tg;
1772 struct dc_context *ctx = dc->ctx;
1773
1774 for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1775 tg = dc->res_pool->timing_generators[i];
1776
1777 if (tg->funcs->disable_vga)
1778 tg->funcs->disable_vga(tg);
1779 }
1780 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1781 /* Enable CLOCK gating for each pipe BEFORE controller
1782 * powergating. */
1783 enable_display_pipe_clock_gating(ctx,
1784 true);
1785
1786 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1787 dc->hwss.disable_plane(dc, dc->current_state,
1788 &dc->current_state->res_ctx.pipe_ctx[i]);
1789 }
1790 }
1791
1792
get_edp_streams(struct dc_state * context,struct dc_stream_state ** edp_streams,int * edp_stream_num)1793 static void get_edp_streams(struct dc_state *context,
1794 struct dc_stream_state **edp_streams,
1795 int *edp_stream_num)
1796 {
1797 int i;
1798
1799 *edp_stream_num = 0;
1800 for (i = 0; i < context->stream_count; i++) {
1801 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1802 edp_streams[*edp_stream_num] = context->streams[i];
1803 if (++(*edp_stream_num) == MAX_NUM_EDP)
1804 return;
1805 }
1806 }
1807 }
1808
get_edp_links_with_sink(struct dc * dc,struct dc_link ** edp_links_with_sink,int * edp_with_sink_num)1809 static void get_edp_links_with_sink(
1810 struct dc *dc,
1811 struct dc_link **edp_links_with_sink,
1812 int *edp_with_sink_num)
1813 {
1814 int i;
1815
1816 /* check if there is an eDP panel not in use */
1817 *edp_with_sink_num = 0;
1818 for (i = 0; i < dc->link_count; i++) {
1819 if (dc->links[i]->local_sink &&
1820 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1821 edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1822 if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1823 return;
1824 }
1825 }
1826 }
1827
clean_up_dsc_blocks(struct dc * dc)1828 static void clean_up_dsc_blocks(struct dc *dc)
1829 {
1830 struct display_stream_compressor *dsc = NULL;
1831 struct timing_generator *tg = NULL;
1832 struct stream_encoder *se = NULL;
1833 struct dccg *dccg = dc->res_pool->dccg;
1834 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
1835 int i;
1836
1837 if (dc->ctx->dce_version != DCN_VERSION_3_5 &&
1838 dc->ctx->dce_version != DCN_VERSION_3_51)
1839 return;
1840
1841 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
1842 struct dcn_dsc_state s = {0};
1843
1844 dsc = dc->res_pool->dscs[i];
1845 dsc->funcs->dsc_read_state(dsc, &s);
1846 if (s.dsc_fw_en) {
1847 /* disable DSC in OPTC */
1848 if (i < dc->res_pool->timing_generator_count) {
1849 tg = dc->res_pool->timing_generators[i];
1850 tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0);
1851 }
1852 /* disable DSC in stream encoder */
1853 if (i < dc->res_pool->stream_enc_count) {
1854 se = dc->res_pool->stream_enc[i];
1855 se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0);
1856 se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true);
1857 }
1858 /* disable DSC block */
1859 if (dccg->funcs->set_ref_dscclk)
1860 dccg->funcs->set_ref_dscclk(dccg, dsc->inst);
1861 dsc->funcs->dsc_disable(dsc);
1862
1863 /* power down DSC */
1864 if (pg_cntl != NULL)
1865 pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false);
1866 }
1867 }
1868 }
1869
1870 /*
1871 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1872 * 1. Power down all DC HW blocks
1873 * 2. Disable VGA engine on all controllers
1874 * 3. Enable power gating for controller
1875 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1876 */
dce110_enable_accelerated_mode(struct dc * dc,struct dc_state * context)1877 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1878 {
1879 struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1880 struct dc_link *edp_links[MAX_NUM_EDP];
1881 struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1882 struct dc_link *edp_link_with_sink = NULL;
1883 struct dc_link *edp_link = NULL;
1884 struct pipe_ctx *pipe_ctx = NULL;
1885 struct dce_hwseq *hws = dc->hwseq;
1886 int edp_with_sink_num;
1887 int edp_num;
1888 int edp_stream_num;
1889 int i;
1890 bool can_apply_edp_fast_boot = false;
1891 bool can_apply_seamless_boot = false;
1892 bool keep_edp_vdd_on = false;
1893 struct dc_bios *dcb = dc->ctx->dc_bios;
1894 DC_LOGGER_INIT();
1895
1896
1897 get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1898 dc_get_edp_links(dc, edp_links, &edp_num);
1899
1900 if (hws->funcs.init_pipes)
1901 hws->funcs.init_pipes(dc, context);
1902
1903 get_edp_streams(context, edp_streams, &edp_stream_num);
1904
1905 // Check fastboot support, disable on DCE8 because of blank screens
1906 if (edp_num && edp_stream_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1907 dc->ctx->dce_version != DCE_VERSION_8_1 &&
1908 dc->ctx->dce_version != DCE_VERSION_8_3) {
1909 for (i = 0; i < edp_num; i++) {
1910 edp_link = edp_links[i];
1911 if (edp_link != edp_streams[0]->link)
1912 continue;
1913 // enable fastboot if backend is enabled on eDP
1914 if (edp_link->link_enc->funcs->is_dig_enabled &&
1915 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
1916 edp_link->link_status.link_active) {
1917 struct dc_stream_state *edp_stream = edp_streams[0];
1918
1919 can_apply_edp_fast_boot = dc_validate_boot_timing(dc,
1920 edp_stream->sink, &edp_stream->timing);
1921 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1922 if (can_apply_edp_fast_boot) {
1923 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot Enable\n");
1924
1925 // Vbios & Driver support different pixel rate div policy.
1926 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream);
1927 if (pipe_ctx &&
1928 hws->funcs.is_dp_dig_pixel_rate_div_policy &&
1929 hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) {
1930 // Get Vbios div factor from register
1931 dc->res_pool->dccg->funcs->get_pixel_rate_div(
1932 dc->res_pool->dccg,
1933 pipe_ctx->stream_res.tg->inst,
1934 &pipe_ctx->pixel_rate_divider.div_factor1,
1935 &pipe_ctx->pixel_rate_divider.div_factor2);
1936
1937 // VBios doesn't support pixel rate div, so force it.
1938 // If VBios supports it, we check it from reigster or other flags.
1939 pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1;
1940 }
1941 }
1942 break;
1943 }
1944 }
1945 // We are trying to enable eDP, don't power down VDD
1946 if (can_apply_edp_fast_boot)
1947 keep_edp_vdd_on = true;
1948 }
1949
1950 // Check seamless boot support
1951 for (i = 0; i < context->stream_count; i++) {
1952 if (context->streams[i]->apply_seamless_boot_optimization) {
1953 can_apply_seamless_boot = true;
1954 break;
1955 }
1956 }
1957
1958 /* eDP should not have stream in resume from S4 and so even with VBios post
1959 * it should get turned off
1960 */
1961 if (edp_with_sink_num)
1962 edp_link_with_sink = edp_links_with_sink[0];
1963
1964 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1965 if (edp_link_with_sink && !keep_edp_vdd_on) {
1966 /*turn off backlight before DP_blank and encoder powered down*/
1967 hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1968 }
1969 /*resume from S3, no vbios posting, no need to power down again*/
1970 if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb))
1971 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1972
1973 power_down_all_hw_blocks(dc);
1974
1975 /* DSC could be enabled on eDP during VBIOS post.
1976 * To clean up dsc blocks if eDP is in link but not active.
1977 */
1978 if (edp_link_with_sink && (edp_stream_num == 0))
1979 clean_up_dsc_blocks(dc);
1980
1981 disable_vga_and_power_gate_all_controllers(dc);
1982 if (edp_link_with_sink && !keep_edp_vdd_on)
1983 dc->hwss.edp_power_control(edp_link_with_sink, false);
1984 if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb))
1985 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1986 }
1987 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1988 }
1989
compute_pstate_blackout_duration(struct bw_fixed blackout_duration,const struct dc_stream_state * stream)1990 static uint32_t compute_pstate_blackout_duration(
1991 struct bw_fixed blackout_duration,
1992 const struct dc_stream_state *stream)
1993 {
1994 uint32_t total_dest_line_time_ns;
1995 uint32_t pstate_blackout_duration_ns;
1996
1997 pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1998
1999 total_dest_line_time_ns = 1000000UL *
2000 (stream->timing.h_total * 10) /
2001 stream->timing.pix_clk_100hz +
2002 pstate_blackout_duration_ns;
2003
2004 return total_dest_line_time_ns;
2005 }
2006
dce110_set_displaymarks(const struct dc * dc,struct dc_state * context)2007 static void dce110_set_displaymarks(
2008 const struct dc *dc,
2009 struct dc_state *context)
2010 {
2011 uint8_t i, num_pipes;
2012 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2013
2014 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
2015 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2016 uint32_t total_dest_line_time_ns;
2017
2018 if (pipe_ctx->stream == NULL)
2019 continue;
2020
2021 total_dest_line_time_ns = compute_pstate_blackout_duration(
2022 dc->bw_vbios->blackout_duration, pipe_ctx->stream);
2023 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
2024 pipe_ctx->plane_res.mi,
2025 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
2026 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
2027 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
2028 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
2029 total_dest_line_time_ns);
2030 if (i == underlay_idx) {
2031 num_pipes++;
2032 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
2033 pipe_ctx->plane_res.mi,
2034 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
2035 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
2036 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
2037 total_dest_line_time_ns);
2038 }
2039 num_pipes++;
2040 }
2041 }
2042
dce110_set_safe_displaymarks(struct resource_context * res_ctx,const struct resource_pool * pool)2043 void dce110_set_safe_displaymarks(
2044 struct resource_context *res_ctx,
2045 const struct resource_pool *pool)
2046 {
2047 int i;
2048 int underlay_idx = pool->underlay_pipe_index;
2049 struct dce_watermarks max_marks = {
2050 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
2051 struct dce_watermarks nbp_marks = {
2052 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
2053 struct dce_watermarks min_marks = { 0, 0, 0, 0};
2054
2055 for (i = 0; i < MAX_PIPES; i++) {
2056 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
2057 continue;
2058
2059 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
2060 res_ctx->pipe_ctx[i].plane_res.mi,
2061 nbp_marks,
2062 max_marks,
2063 min_marks,
2064 max_marks,
2065 MAX_WATERMARK);
2066
2067 if (i == underlay_idx)
2068 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
2069 res_ctx->pipe_ctx[i].plane_res.mi,
2070 nbp_marks,
2071 max_marks,
2072 max_marks,
2073 MAX_WATERMARK);
2074
2075 }
2076 }
2077
2078 /*******************************************************************************
2079 * Public functions
2080 ******************************************************************************/
2081
set_drr(struct pipe_ctx ** pipe_ctx,int num_pipes,struct dc_crtc_timing_adjust adjust)2082 static void set_drr(struct pipe_ctx **pipe_ctx,
2083 int num_pipes, struct dc_crtc_timing_adjust adjust)
2084 {
2085 int i = 0;
2086 struct drr_params params = {0};
2087 // DRR should set trigger event to monitor surface update event
2088 unsigned int event_triggers = 0x80;
2089 // Note DRR trigger events are generated regardless of whether num frames met.
2090 unsigned int num_frames = 2;
2091
2092 params.vertical_total_max = adjust.v_total_max;
2093 params.vertical_total_min = adjust.v_total_min;
2094
2095 /* TODO: If multiple pipes are to be supported, you need
2096 * some GSL stuff. Static screen triggers may be programmed differently
2097 * as well.
2098 */
2099 for (i = 0; i < num_pipes; i++) {
2100 /* dc_state_destruct() might null the stream resources, so fetch tg
2101 * here first to avoid a race condition. The lifetime of the pointee
2102 * itself (the timing_generator object) is not a problem here.
2103 */
2104 struct timing_generator *tg = pipe_ctx[i]->stream_res.tg;
2105
2106 if ((tg != NULL) && tg->funcs) {
2107 if (tg->funcs->set_drr)
2108 tg->funcs->set_drr(tg, ¶ms);
2109 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
2110 if (tg->funcs->set_static_screen_control)
2111 tg->funcs->set_static_screen_control(
2112 tg, event_triggers, num_frames);
2113 }
2114 }
2115 }
2116
get_position(struct pipe_ctx ** pipe_ctx,int num_pipes,struct crtc_position * position)2117 static void get_position(struct pipe_ctx **pipe_ctx,
2118 int num_pipes,
2119 struct crtc_position *position)
2120 {
2121 int i = 0;
2122
2123 /* TODO: handle pipes > 1
2124 */
2125 for (i = 0; i < num_pipes; i++)
2126 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2127 }
2128
set_static_screen_control(struct pipe_ctx ** pipe_ctx,int num_pipes,const struct dc_static_screen_params * params)2129 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2130 int num_pipes, const struct dc_static_screen_params *params)
2131 {
2132 unsigned int i;
2133 unsigned int triggers = 0;
2134
2135 if (params->triggers.overlay_update)
2136 triggers |= 0x100;
2137 if (params->triggers.surface_update)
2138 triggers |= 0x80;
2139 if (params->triggers.cursor_update)
2140 triggers |= 0x2;
2141 if (params->triggers.force_trigger)
2142 triggers |= 0x1;
2143
2144 if (num_pipes) {
2145 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
2146
2147 if (dc->fbc_compressor)
2148 triggers |= 0x84;
2149 }
2150
2151 for (i = 0; i < num_pipes; i++)
2152 pipe_ctx[i]->stream_res.tg->funcs->
2153 set_static_screen_control(pipe_ctx[i]->stream_res.tg,
2154 triggers, params->num_frames);
2155 }
2156
2157 /*
2158 * Check if FBC can be enabled
2159 */
should_enable_fbc(struct dc * dc,struct dc_state * context,uint32_t * pipe_idx)2160 static bool should_enable_fbc(struct dc *dc,
2161 struct dc_state *context,
2162 uint32_t *pipe_idx)
2163 {
2164 uint32_t i;
2165 struct pipe_ctx *pipe_ctx = NULL;
2166 struct resource_context *res_ctx = &context->res_ctx;
2167 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
2168
2169
2170 ASSERT(dc->fbc_compressor);
2171
2172 /* FBC memory should be allocated */
2173 if (!dc->ctx->fbc_gpu_addr)
2174 return false;
2175
2176 /* Only supports single display */
2177 if (context->stream_count != 1)
2178 return false;
2179
2180 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2181 if (res_ctx->pipe_ctx[i].stream) {
2182
2183 pipe_ctx = &res_ctx->pipe_ctx[i];
2184
2185 /* fbc not applicable on underlay pipe */
2186 if (pipe_ctx->pipe_idx != underlay_idx) {
2187 *pipe_idx = i;
2188 break;
2189 }
2190 }
2191 }
2192
2193 if (i == dc->res_pool->pipe_count)
2194 return false;
2195
2196 if (!pipe_ctx->stream->link)
2197 return false;
2198
2199 /* Only supports eDP */
2200 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
2201 return false;
2202
2203 /* PSR should not be enabled */
2204 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
2205 return false;
2206
2207 /* Replay should not be enabled */
2208 if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled)
2209 return false;
2210
2211 /* Nothing to compress */
2212 if (!pipe_ctx->plane_state)
2213 return false;
2214
2215 /* Only for non-linear tiling */
2216 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
2217 return false;
2218
2219 return true;
2220 }
2221
2222 /*
2223 * Enable FBC
2224 */
enable_fbc(struct dc * dc,struct dc_state * context)2225 static void enable_fbc(
2226 struct dc *dc,
2227 struct dc_state *context)
2228 {
2229 uint32_t pipe_idx = 0;
2230
2231 if (should_enable_fbc(dc, context, &pipe_idx)) {
2232 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2233 struct compr_addr_and_pitch_params params = {0, 0, 0};
2234 struct compressor *compr = dc->fbc_compressor;
2235 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2236
2237 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2238 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2239 params.inst = pipe_ctx->stream_res.tg->inst;
2240 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2241
2242 compr->funcs->surface_address_and_pitch(compr, ¶ms);
2243 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2244
2245 compr->funcs->enable_fbc(compr, ¶ms);
2246 }
2247 }
2248
dce110_reset_hw_ctx_wrap(struct dc * dc,struct dc_state * context)2249 static void dce110_reset_hw_ctx_wrap(
2250 struct dc *dc,
2251 struct dc_state *context)
2252 {
2253 int i;
2254
2255 /* Reset old context */
2256 /* look up the targets that have been removed since last commit */
2257 for (i = 0; i < MAX_PIPES; i++) {
2258 struct pipe_ctx *pipe_ctx_old =
2259 &dc->current_state->res_ctx.pipe_ctx[i];
2260 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2261
2262 /* Note: We need to disable output if clock sources change,
2263 * since bios does optimization and doesn't apply if changing
2264 * PHY when not already disabled.
2265 */
2266
2267 /* Skip underlay pipe since it will be handled in commit surface*/
2268 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2269 continue;
2270
2271 if (!pipe_ctx->stream ||
2272 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2273 struct clock_source *old_clk = pipe_ctx_old->clock_source;
2274
2275 /* Disable if new stream is null. O/w, if stream is
2276 * disabled already, no need to disable again.
2277 */
2278 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2279 dc->link_srv->set_dpms_off(pipe_ctx_old);
2280
2281 /* free acquired resources*/
2282 if (pipe_ctx_old->stream_res.audio) {
2283 /*disable az_endpoint*/
2284 pipe_ctx_old->stream_res.audio->funcs->
2285 az_disable(pipe_ctx_old->stream_res.audio);
2286
2287 /*free audio*/
2288 if (dc->caps.dynamic_audio == true) {
2289 /*we have to dynamic arbitrate the audio endpoints*/
2290 /*we free the resource, need reset is_audio_acquired*/
2291 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2292 pipe_ctx_old->stream_res.audio, false);
2293 pipe_ctx_old->stream_res.audio = NULL;
2294 }
2295 }
2296 }
2297
2298 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2299 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2300 dm_error("DC: failed to blank crtc!\n");
2301 BREAK_TO_DEBUGGER();
2302 }
2303 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2304 if (dc_is_hdmi_tmds_signal(pipe_ctx_old->stream->signal))
2305 pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0;
2306 pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2307 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2308
2309 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2310 dc->res_pool,
2311 old_clk))
2312 old_clk->funcs->cs_power_down(old_clk);
2313
2314 dc->hwss.disable_plane(dc, dc->current_state, pipe_ctx_old);
2315
2316 pipe_ctx_old->stream = NULL;
2317 }
2318 }
2319 }
2320
dce110_setup_audio_dto(struct dc * dc,struct dc_state * context)2321 static void dce110_setup_audio_dto(
2322 struct dc *dc,
2323 struct dc_state *context)
2324 {
2325 unsigned int i;
2326
2327 /* program audio wall clock. use HDMI as clock source if HDMI
2328 * audio active. Otherwise, use DP as clock source
2329 * first, loop to find any HDMI audio, if not, loop find DP audio
2330 */
2331 /* Setup audio rate clock source */
2332 /* Issue:
2333 * Audio lag happened on DP monitor when unplug a HDMI monitor
2334 *
2335 * Cause:
2336 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2337 * is set to either dto0 or dto1, audio should work fine.
2338 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2339 * set to dto0 will cause audio lag.
2340 *
2341 * Solution:
2342 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2343 * find first available pipe with audio, setup audio wall DTO per topology
2344 * instead of per pipe.
2345 */
2346 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2347 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2348
2349 if (pipe_ctx->stream == NULL)
2350 continue;
2351
2352 if (pipe_ctx->top_pipe)
2353 continue;
2354 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2355 continue;
2356 if (pipe_ctx->stream_res.audio != NULL) {
2357 struct audio_output audio_output;
2358
2359 build_audio_output(context, pipe_ctx, &audio_output);
2360
2361 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
2362 struct dtbclk_dto_params dto_params = {0};
2363
2364 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
2365 dc->res_pool->dccg, &dto_params);
2366
2367 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2368 pipe_ctx->stream_res.audio,
2369 pipe_ctx->stream->signal,
2370 &audio_output.crtc_info,
2371 &audio_output.pll_info);
2372 } else
2373 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2374 pipe_ctx->stream_res.audio,
2375 pipe_ctx->stream->signal,
2376 &audio_output.crtc_info,
2377 &audio_output.pll_info);
2378 break;
2379 }
2380 }
2381
2382 /* no HDMI audio is found, try DP audio */
2383 if (i == dc->res_pool->pipe_count) {
2384 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2385 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2386
2387 if (pipe_ctx->stream == NULL)
2388 continue;
2389
2390 if (pipe_ctx->top_pipe)
2391 continue;
2392
2393 if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2394 continue;
2395
2396 if (pipe_ctx->stream_res.audio != NULL) {
2397 struct audio_output audio_output = {0};
2398
2399 build_audio_output(context, pipe_ctx, &audio_output);
2400
2401 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2402 pipe_ctx->stream_res.audio,
2403 pipe_ctx->stream->signal,
2404 &audio_output.crtc_info,
2405 &audio_output.pll_info);
2406 break;
2407 }
2408 }
2409 }
2410 }
2411
dce110_apply_ctx_to_hw(struct dc * dc,struct dc_state * context)2412 enum dc_status dce110_apply_ctx_to_hw(
2413 struct dc *dc,
2414 struct dc_state *context)
2415 {
2416 struct dce_hwseq *hws = dc->hwseq;
2417 struct dc_bios *dcb = dc->ctx->dc_bios;
2418 enum dc_status status;
2419 int i;
2420 bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state);
2421 bool is_hpo_acquired = resource_is_hpo_acquired(context);
2422
2423 /* reset syncd pipes from disabled pipes */
2424 if (dc->config.use_pipe_ctx_sync_logic)
2425 reset_syncd_pipes_from_disabled_pipes(dc, context);
2426
2427 /* Reset old context */
2428 /* look up the targets that have been removed since last commit */
2429 hws->funcs.reset_hw_ctx_wrap(dc, context);
2430
2431 /* Skip applying if no targets */
2432 if (context->stream_count <= 0)
2433 return DC_OK;
2434
2435 /* Apply new context */
2436 dcb->funcs->set_scratch_critical_state(dcb, true);
2437
2438 /* below is for real asic only */
2439 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2440 struct pipe_ctx *pipe_ctx_old =
2441 &dc->current_state->res_ctx.pipe_ctx[i];
2442 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2443
2444 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2445 continue;
2446
2447 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2448 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2449 dce_crtc_switch_to_clk_src(dc->hwseq,
2450 pipe_ctx->clock_source, i);
2451 continue;
2452 }
2453
2454 hws->funcs.enable_display_power_gating(
2455 dc, i, dc->ctx->dc_bios,
2456 PIPE_GATING_CONTROL_DISABLE);
2457 }
2458
2459 if (dc->fbc_compressor)
2460 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2461
2462 dce110_setup_audio_dto(dc, context);
2463
2464 if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) {
2465 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired);
2466 }
2467
2468 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2469 struct pipe_ctx *pipe_ctx_old =
2470 &dc->current_state->res_ctx.pipe_ctx[i];
2471 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2472
2473 if (pipe_ctx->stream == NULL)
2474 continue;
2475
2476 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2477 pipe_ctx->stream->link->link_state_valid) {
2478 continue;
2479 }
2480
2481 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2482 continue;
2483
2484 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2485 continue;
2486
2487 status = dce110_apply_single_controller_ctx_to_hw(
2488 pipe_ctx,
2489 context,
2490 dc);
2491
2492 if (DC_OK != status)
2493 return status;
2494
2495 #ifdef CONFIG_DRM_AMD_DC_FP
2496 if (hws->funcs.resync_fifo_dccg_dio)
2497 hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i);
2498 #endif
2499 }
2500
2501 if (dc->fbc_compressor)
2502 enable_fbc(dc, dc->current_state);
2503
2504 dcb->funcs->set_scratch_critical_state(dcb, false);
2505
2506 return DC_OK;
2507 }
2508
2509 /*******************************************************************************
2510 * Front End programming
2511 ******************************************************************************/
set_default_colors(struct pipe_ctx * pipe_ctx)2512 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2513 {
2514 struct default_adjustment default_adjust = { 0 };
2515
2516 default_adjust.force_hw_default = false;
2517 default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2518 default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2519 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2520 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2521
2522 /* display color depth */
2523 default_adjust.color_depth =
2524 pipe_ctx->stream->timing.display_color_depth;
2525
2526 /* Lb color depth */
2527 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2528
2529 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2530 pipe_ctx->plane_res.xfm, &default_adjust);
2531 }
2532
2533
2534 /*******************************************************************************
2535 * In order to turn on/off specific surface we will program
2536 * Blender + CRTC
2537 *
2538 * In case that we have two surfaces and they have a different visibility
2539 * we can't turn off the CRTC since it will turn off the entire display
2540 *
2541 * |----------------------------------------------- |
2542 * |bottom pipe|curr pipe | | |
2543 * |Surface |Surface | Blender | CRCT |
2544 * |visibility |visibility | Configuration| |
2545 * |------------------------------------------------|
2546 * | off | off | CURRENT_PIPE | blank |
2547 * | off | on | CURRENT_PIPE | unblank |
2548 * | on | off | OTHER_PIPE | unblank |
2549 * | on | on | BLENDING | unblank |
2550 * -------------------------------------------------|
2551 *
2552 ******************************************************************************/
program_surface_visibility(const struct dc * dc,struct pipe_ctx * pipe_ctx)2553 static void program_surface_visibility(const struct dc *dc,
2554 struct pipe_ctx *pipe_ctx)
2555 {
2556 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2557 bool blank_target = false;
2558
2559 if (pipe_ctx->bottom_pipe) {
2560
2561 /* For now we are supporting only two pipes */
2562 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2563
2564 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2565 if (pipe_ctx->plane_state->visible)
2566 blender_mode = BLND_MODE_BLENDING;
2567 else
2568 blender_mode = BLND_MODE_OTHER_PIPE;
2569
2570 } else if (!pipe_ctx->plane_state->visible)
2571 blank_target = true;
2572
2573 } else if (!pipe_ctx->plane_state->visible)
2574 blank_target = true;
2575
2576 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2577 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2578
2579 }
2580
program_gamut_remap(struct pipe_ctx * pipe_ctx)2581 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2582 {
2583 int i = 0;
2584 struct xfm_grph_csc_adjustment adjust;
2585 memset(&adjust, 0, sizeof(adjust));
2586 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2587
2588
2589 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2590 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2591
2592 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2593 adjust.temperature_matrix[i] =
2594 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2595 }
2596
2597 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2598 }
update_plane_addr(const struct dc * dc,struct pipe_ctx * pipe_ctx)2599 static void update_plane_addr(const struct dc *dc,
2600 struct pipe_ctx *pipe_ctx)
2601 {
2602 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2603
2604 if (plane_state == NULL)
2605 return;
2606
2607 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2608 pipe_ctx->plane_res.mi,
2609 &plane_state->address,
2610 plane_state->flip_immediate);
2611
2612 plane_state->status.requested_address = plane_state->address;
2613 }
2614
dce110_update_pending_status(struct pipe_ctx * pipe_ctx)2615 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2616 {
2617 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2618
2619 if (plane_state == NULL)
2620 return;
2621
2622 plane_state->status.is_flip_pending =
2623 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2624 pipe_ctx->plane_res.mi);
2625
2626 if (plane_state->status.is_flip_pending && !plane_state->visible)
2627 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2628
2629 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2630 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2631 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2632 plane_state->status.is_right_eye =\
2633 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2634 }
2635 }
2636
dce110_power_down(struct dc * dc)2637 void dce110_power_down(struct dc *dc)
2638 {
2639 power_down_all_hw_blocks(dc);
2640 disable_vga_and_power_gate_all_controllers(dc);
2641 }
2642
wait_for_reset_trigger_to_occur(struct dc_context * dc_ctx,struct timing_generator * tg)2643 static bool wait_for_reset_trigger_to_occur(
2644 struct dc_context *dc_ctx,
2645 struct timing_generator *tg)
2646 {
2647 struct dc_context *ctx = dc_ctx;
2648 bool rc = false;
2649
2650 /* To avoid endless loop we wait at most
2651 * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2652 const uint32_t frames_to_wait_on_triggered_reset = 10;
2653 uint32_t i;
2654
2655 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2656
2657 if (!tg->funcs->is_counter_moving(tg)) {
2658 DC_ERROR("TG counter is not moving!\n");
2659 break;
2660 }
2661
2662 if (tg->funcs->did_triggered_reset_occur(tg)) {
2663 rc = true;
2664 /* usually occurs at i=1 */
2665 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2666 i);
2667 break;
2668 }
2669
2670 /* Wait for one frame. */
2671 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2672 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2673 }
2674
2675 if (false == rc)
2676 DC_ERROR("GSL: Timeout on reset trigger!\n");
2677
2678 return rc;
2679 }
2680
2681 /* Enable timing synchronization for a group of Timing Generators. */
dce110_enable_timing_synchronization(struct dc * dc,struct dc_state * state,int group_index,int group_size,struct pipe_ctx * grouped_pipes[])2682 static void dce110_enable_timing_synchronization(
2683 struct dc *dc,
2684 struct dc_state *state,
2685 int group_index,
2686 int group_size,
2687 struct pipe_ctx *grouped_pipes[])
2688 {
2689 struct dc_context *dc_ctx = dc->ctx;
2690 struct dcp_gsl_params gsl_params = { 0 };
2691 int i;
2692 DC_LOGGER_INIT();
2693
2694 DC_SYNC_INFO("GSL: Setting-up...\n");
2695
2696 /* Designate a single TG in the group as a master.
2697 * Since HW doesn't care which one, we always assign
2698 * the 1st one in the group. */
2699 gsl_params.gsl_group = 0;
2700 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2701
2702 for (i = 0; i < group_size; i++)
2703 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2704 grouped_pipes[i]->stream_res.tg, &gsl_params);
2705
2706 /* Reset slave controllers on master VSync */
2707 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2708
2709 for (i = 1 /* skip the master */; i < group_size; i++)
2710 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2711 grouped_pipes[i]->stream_res.tg,
2712 gsl_params.gsl_group);
2713
2714 for (i = 1 /* skip the master */; i < group_size; i++) {
2715 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2716 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2717 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2718 grouped_pipes[i]->stream_res.tg);
2719 }
2720
2721 /* GSL Vblank synchronization is a one time sync mechanism, assumption
2722 * is that the sync'ed displays will not drift out of sync over time*/
2723 DC_SYNC_INFO("GSL: Restoring register states.\n");
2724 for (i = 0; i < group_size; i++)
2725 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2726
2727 DC_SYNC_INFO("GSL: Set-up complete.\n");
2728 }
2729
dce110_enable_per_frame_crtc_position_reset(struct dc * dc,int group_size,struct pipe_ctx * grouped_pipes[])2730 static void dce110_enable_per_frame_crtc_position_reset(
2731 struct dc *dc,
2732 int group_size,
2733 struct pipe_ctx *grouped_pipes[])
2734 {
2735 struct dc_context *dc_ctx = dc->ctx;
2736 struct dcp_gsl_params gsl_params = { 0 };
2737 int i;
2738 DC_LOGGER_INIT();
2739
2740 gsl_params.gsl_group = 0;
2741 gsl_params.gsl_master = 0;
2742
2743 for (i = 0; i < group_size; i++)
2744 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2745 grouped_pipes[i]->stream_res.tg, &gsl_params);
2746
2747 DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2748
2749 for (i = 1; i < group_size; i++)
2750 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2751 grouped_pipes[i]->stream_res.tg,
2752 gsl_params.gsl_master,
2753 &grouped_pipes[i]->stream->triggered_crtc_reset);
2754
2755 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2756 for (i = 1; i < group_size; i++)
2757 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2758
2759 for (i = 0; i < group_size; i++)
2760 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2761
2762 }
2763
init_pipes(struct dc * dc,struct dc_state * context)2764 static void init_pipes(struct dc *dc, struct dc_state *context)
2765 {
2766 // Do nothing
2767 }
2768
init_hw(struct dc * dc)2769 static void init_hw(struct dc *dc)
2770 {
2771 int i;
2772 struct dc_bios *bp;
2773 struct transform *xfm;
2774 struct abm *abm;
2775 struct dmcu *dmcu;
2776 struct dce_hwseq *hws = dc->hwseq;
2777 uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2778 uint32_t user_level = MAX_BACKLIGHT_LEVEL;
2779
2780 bp = dc->ctx->dc_bios;
2781 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2782 xfm = dc->res_pool->transforms[i];
2783 xfm->funcs->transform_reset(xfm);
2784
2785 hws->funcs.enable_display_power_gating(
2786 dc, i, bp,
2787 PIPE_GATING_CONTROL_INIT);
2788 hws->funcs.enable_display_power_gating(
2789 dc, i, bp,
2790 PIPE_GATING_CONTROL_DISABLE);
2791 hws->funcs.enable_display_pipe_clock_gating(
2792 dc->ctx,
2793 true);
2794 }
2795
2796 dce_clock_gating_power_up(dc->hwseq, false);
2797 /***************************************/
2798
2799 for (i = 0; i < dc->link_count; i++) {
2800 /****************************************/
2801 /* Power up AND update implementation according to the
2802 * required signal (which may be different from the
2803 * default signal on connector). */
2804 struct dc_link *link = dc->links[i];
2805
2806 link->link_enc->funcs->hw_init(link->link_enc);
2807 }
2808
2809 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2810 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2811
2812 tg->funcs->disable_vga(tg);
2813
2814 /* Blank controller using driver code instead of
2815 * command table. */
2816 tg->funcs->set_blank(tg, true);
2817 hwss_wait_for_blank_complete(tg);
2818 }
2819
2820 for (i = 0; i < dc->res_pool->audio_count; i++) {
2821 struct audio *audio = dc->res_pool->audios[i];
2822 audio->funcs->hw_init(audio);
2823 }
2824
2825 for (i = 0; i < dc->link_count; i++) {
2826 struct dc_link *link = dc->links[i];
2827
2828 if (link->panel_cntl) {
2829 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2830 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL;
2831 }
2832 }
2833
2834 abm = dc->res_pool->abm;
2835 if (abm != NULL)
2836 abm->funcs->abm_init(abm, backlight, user_level);
2837
2838 dmcu = dc->res_pool->dmcu;
2839 if (dmcu != NULL && abm != NULL)
2840 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2841
2842 if (dc->fbc_compressor)
2843 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2844
2845 }
2846
2847
dce110_prepare_bandwidth(struct dc * dc,struct dc_state * context)2848 void dce110_prepare_bandwidth(
2849 struct dc *dc,
2850 struct dc_state *context)
2851 {
2852 struct clk_mgr *dccg = dc->clk_mgr;
2853
2854 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2855 if (dccg)
2856 dccg->funcs->update_clocks(
2857 dccg,
2858 context,
2859 false);
2860 }
2861
dce110_optimize_bandwidth(struct dc * dc,struct dc_state * context)2862 void dce110_optimize_bandwidth(
2863 struct dc *dc,
2864 struct dc_state *context)
2865 {
2866 struct clk_mgr *dccg = dc->clk_mgr;
2867
2868 dce110_set_displaymarks(dc, context);
2869
2870 if (dccg)
2871 dccg->funcs->update_clocks(
2872 dccg,
2873 context,
2874 true);
2875 }
2876
dce110_program_front_end_for_pipe(struct dc * dc,struct pipe_ctx * pipe_ctx)2877 static void dce110_program_front_end_for_pipe(
2878 struct dc *dc, struct pipe_ctx *pipe_ctx)
2879 {
2880 struct mem_input *mi = pipe_ctx->plane_res.mi;
2881 struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2882 struct xfm_grph_csc_adjustment adjust;
2883 struct out_csc_color_matrix tbl_entry;
2884 unsigned int i;
2885 struct dce_hwseq *hws = dc->hwseq;
2886
2887 memset(&tbl_entry, 0, sizeof(tbl_entry));
2888
2889 memset(&adjust, 0, sizeof(adjust));
2890 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2891
2892 dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2893
2894 set_default_colors(pipe_ctx);
2895 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2896 == true) {
2897 tbl_entry.color_space =
2898 pipe_ctx->stream->output_color_space;
2899
2900 for (i = 0; i < 12; i++)
2901 tbl_entry.regval[i] =
2902 pipe_ctx->stream->csc_color_matrix.matrix[i];
2903
2904 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2905 (pipe_ctx->plane_res.xfm, &tbl_entry);
2906 }
2907
2908 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2909 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2910
2911 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2912 adjust.temperature_matrix[i] =
2913 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2914 }
2915
2916 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2917
2918 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
2919
2920 program_scaler(dc, pipe_ctx);
2921
2922 mi->funcs->mem_input_program_surface_config(
2923 mi,
2924 plane_state->format,
2925 &plane_state->tiling_info,
2926 &plane_state->plane_size,
2927 plane_state->rotation,
2928 NULL,
2929 false);
2930 if (mi->funcs->set_blank)
2931 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2932
2933 if (dc->config.gpu_vm_support)
2934 mi->funcs->mem_input_program_pte_vm(
2935 pipe_ctx->plane_res.mi,
2936 plane_state->format,
2937 &plane_state->tiling_info,
2938 plane_state->rotation);
2939
2940 /* Moved programming gamma from dc to hwss */
2941 if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2942 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2943 pipe_ctx->plane_state->update_flags.bits.gamma_change)
2944 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2945
2946 if (pipe_ctx->plane_state->update_flags.bits.full_update)
2947 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2948
2949 DC_LOG_SURFACE(
2950 "Pipe:%d %p: addr hi:0x%x, "
2951 "addr low:0x%x, "
2952 "src: %d, %d, %d,"
2953 " %d; dst: %d, %d, %d, %d;"
2954 "clip: %d, %d, %d, %d\n",
2955 pipe_ctx->pipe_idx,
2956 (void *) pipe_ctx->plane_state,
2957 pipe_ctx->plane_state->address.grph.addr.high_part,
2958 pipe_ctx->plane_state->address.grph.addr.low_part,
2959 pipe_ctx->plane_state->src_rect.x,
2960 pipe_ctx->plane_state->src_rect.y,
2961 pipe_ctx->plane_state->src_rect.width,
2962 pipe_ctx->plane_state->src_rect.height,
2963 pipe_ctx->plane_state->dst_rect.x,
2964 pipe_ctx->plane_state->dst_rect.y,
2965 pipe_ctx->plane_state->dst_rect.width,
2966 pipe_ctx->plane_state->dst_rect.height,
2967 pipe_ctx->plane_state->clip_rect.x,
2968 pipe_ctx->plane_state->clip_rect.y,
2969 pipe_ctx->plane_state->clip_rect.width,
2970 pipe_ctx->plane_state->clip_rect.height);
2971
2972 DC_LOG_SURFACE(
2973 "Pipe %d: width, height, x, y\n"
2974 "viewport:%d, %d, %d, %d\n"
2975 "recout: %d, %d, %d, %d\n",
2976 pipe_ctx->pipe_idx,
2977 pipe_ctx->plane_res.scl_data.viewport.width,
2978 pipe_ctx->plane_res.scl_data.viewport.height,
2979 pipe_ctx->plane_res.scl_data.viewport.x,
2980 pipe_ctx->plane_res.scl_data.viewport.y,
2981 pipe_ctx->plane_res.scl_data.recout.width,
2982 pipe_ctx->plane_res.scl_data.recout.height,
2983 pipe_ctx->plane_res.scl_data.recout.x,
2984 pipe_ctx->plane_res.scl_data.recout.y);
2985 }
2986
dce110_apply_ctx_for_surface(struct dc * dc,const struct dc_stream_state * stream,int num_planes,struct dc_state * context)2987 static void dce110_apply_ctx_for_surface(
2988 struct dc *dc,
2989 const struct dc_stream_state *stream,
2990 int num_planes,
2991 struct dc_state *context)
2992 {
2993 int i;
2994
2995 if (num_planes == 0)
2996 return;
2997
2998 if (dc->fbc_compressor)
2999 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
3000
3001 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3002 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
3003
3004 if (pipe_ctx->stream != stream)
3005 continue;
3006
3007 /* Need to allocate mem before program front end for Fiji */
3008 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
3009 pipe_ctx->plane_res.mi,
3010 pipe_ctx->stream->timing.h_total,
3011 pipe_ctx->stream->timing.v_total,
3012 pipe_ctx->stream->timing.pix_clk_100hz / 10,
3013 context->stream_count);
3014
3015 dce110_program_front_end_for_pipe(dc, pipe_ctx);
3016
3017 dc->hwss.update_plane_addr(dc, pipe_ctx);
3018
3019 program_surface_visibility(dc, pipe_ctx);
3020
3021 }
3022
3023 if (dc->fbc_compressor)
3024 enable_fbc(dc, context);
3025 }
3026
dce110_post_unlock_program_front_end(struct dc * dc,struct dc_state * context)3027 static void dce110_post_unlock_program_front_end(
3028 struct dc *dc,
3029 struct dc_state *context)
3030 {
3031 }
3032
dce110_power_down_fe(struct dc * dc,struct dc_state * state,struct pipe_ctx * pipe_ctx)3033 static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx)
3034 {
3035 struct dce_hwseq *hws = dc->hwseq;
3036 int fe_idx = pipe_ctx->plane_res.mi ?
3037 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
3038
3039 /* Do not power down fe when stream is active on dce*/
3040 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
3041 return;
3042
3043 hws->funcs.enable_display_power_gating(
3044 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
3045
3046 dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
3047 dc->res_pool->transforms[fe_idx]);
3048 }
3049
dce110_wait_for_mpcc_disconnect(struct dc * dc,struct resource_pool * res_pool,struct pipe_ctx * pipe_ctx)3050 static void dce110_wait_for_mpcc_disconnect(
3051 struct dc *dc,
3052 struct resource_pool *res_pool,
3053 struct pipe_ctx *pipe_ctx)
3054 {
3055 /* do nothing*/
3056 }
3057
program_output_csc(struct dc * dc,struct pipe_ctx * pipe_ctx,enum dc_color_space colorspace,uint16_t * matrix,int opp_id)3058 static void program_output_csc(struct dc *dc,
3059 struct pipe_ctx *pipe_ctx,
3060 enum dc_color_space colorspace,
3061 uint16_t *matrix,
3062 int opp_id)
3063 {
3064 int i;
3065 struct out_csc_color_matrix tbl_entry;
3066
3067 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
3068 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
3069
3070 for (i = 0; i < 12; i++)
3071 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
3072
3073 tbl_entry.color_space = color_space;
3074
3075 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
3076 pipe_ctx->plane_res.xfm, &tbl_entry);
3077 }
3078 }
3079
dce110_set_cursor_position(struct pipe_ctx * pipe_ctx)3080 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
3081 {
3082 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
3083 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
3084 struct mem_input *mi = pipe_ctx->plane_res.mi;
3085 struct dc_cursor_mi_param param = {
3086 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
3087 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
3088 .viewport = pipe_ctx->plane_res.scl_data.viewport,
3089 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
3090 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
3091 .rotation = pipe_ctx->plane_state->rotation,
3092 .mirror = pipe_ctx->plane_state->horizontal_mirror
3093 };
3094
3095 /**
3096 * If the cursor's source viewport is clipped then we need to
3097 * translate the cursor to appear in the correct position on
3098 * the screen.
3099 *
3100 * This translation isn't affected by scaling so it needs to be
3101 * done *after* we adjust the position for the scale factor.
3102 *
3103 * This is only done by opt-in for now since there are still
3104 * some usecases like tiled display that might enable the
3105 * cursor on both streams while expecting dc to clip it.
3106 */
3107 if (pos_cpy.translate_by_source) {
3108 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
3109 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
3110 }
3111
3112 if (pipe_ctx->plane_state->address.type
3113 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
3114 pos_cpy.enable = false;
3115
3116 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
3117 pos_cpy.enable = false;
3118
3119 if (ipp->funcs->ipp_cursor_set_position)
3120 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m);
3121 if (mi->funcs->set_cursor_position)
3122 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m);
3123 }
3124
dce110_set_cursor_attribute(struct pipe_ctx * pipe_ctx)3125 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
3126 {
3127 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
3128
3129 if (pipe_ctx->plane_res.ipp &&
3130 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
3131 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
3132 pipe_ctx->plane_res.ipp, attributes);
3133
3134 if (pipe_ctx->plane_res.mi &&
3135 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
3136 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
3137 pipe_ctx->plane_res.mi, attributes);
3138
3139 if (pipe_ctx->plane_res.xfm &&
3140 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
3141 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
3142 pipe_ctx->plane_res.xfm, attributes);
3143 }
3144
dce110_set_backlight_level(struct pipe_ctx * pipe_ctx,struct set_backlight_level_params * backlight_level_params)3145 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
3146 struct set_backlight_level_params *backlight_level_params)
3147 {
3148 uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;
3149 uint32_t frame_ramp = backlight_level_params->frame_ramp;
3150 struct dc_link *link = pipe_ctx->stream->link;
3151 struct dc *dc = link->ctx->dc;
3152 struct abm *abm = pipe_ctx->stream_res.abm;
3153 struct panel_cntl *panel_cntl = link->panel_cntl;
3154 struct dmcu *dmcu = dc->res_pool->dmcu;
3155 bool fw_set_brightness = true;
3156 /* DMCU -1 for all controller id values,
3157 * therefore +1 here
3158 */
3159 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
3160
3161 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
3162 return false;
3163
3164 if (dmcu)
3165 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3166
3167 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
3168 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
3169 else
3170 abm->funcs->set_backlight_level_pwm(
3171 abm,
3172 backlight_pwm_u16_16,
3173 frame_ramp,
3174 controller_id,
3175 link->panel_cntl->inst);
3176
3177 return true;
3178 }
3179
dce110_set_abm_immediate_disable(struct pipe_ctx * pipe_ctx)3180 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
3181 {
3182 struct abm *abm = pipe_ctx->stream_res.abm;
3183 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3184
3185 if (abm)
3186 abm->funcs->set_abm_immediate_disable(abm,
3187 pipe_ctx->stream->link->panel_cntl->inst);
3188
3189 if (panel_cntl)
3190 panel_cntl->funcs->store_backlight_level(panel_cntl);
3191 }
3192
dce110_set_pipe(struct pipe_ctx * pipe_ctx)3193 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
3194 {
3195 struct abm *abm = pipe_ctx->stream_res.abm;
3196 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
3197 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
3198
3199 if (abm && panel_cntl)
3200 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
3201 }
3202
dce110_enable_lvds_link_output(struct dc_link * link,const struct link_resource * link_res,enum clock_source_id clock_source,uint32_t pixel_clock)3203 void dce110_enable_lvds_link_output(struct dc_link *link,
3204 const struct link_resource *link_res,
3205 enum clock_source_id clock_source,
3206 uint32_t pixel_clock)
3207 {
3208 link->link_enc->funcs->enable_lvds_output(
3209 link->link_enc,
3210 clock_source,
3211 pixel_clock);
3212 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3213 }
3214
dce110_enable_tmds_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal,enum clock_source_id clock_source,enum dc_color_depth color_depth,uint32_t pixel_clock)3215 void dce110_enable_tmds_link_output(struct dc_link *link,
3216 const struct link_resource *link_res,
3217 enum signal_type signal,
3218 enum clock_source_id clock_source,
3219 enum dc_color_depth color_depth,
3220 uint32_t pixel_clock)
3221 {
3222 link->link_enc->funcs->enable_tmds_output(
3223 link->link_enc,
3224 clock_source,
3225 color_depth,
3226 signal,
3227 pixel_clock);
3228 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3229 }
3230
dce110_enable_dp_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal,enum clock_source_id clock_source,const struct dc_link_settings * link_settings)3231 void dce110_enable_dp_link_output(
3232 struct dc_link *link,
3233 const struct link_resource *link_res,
3234 enum signal_type signal,
3235 enum clock_source_id clock_source,
3236 const struct dc_link_settings *link_settings)
3237 {
3238 struct dc *dc = link->ctx->dc;
3239 struct dmcu *dmcu = dc->res_pool->dmcu;
3240 struct pipe_ctx *pipes =
3241 link->dc->current_state->res_ctx.pipe_ctx;
3242 struct clock_source *dp_cs =
3243 link->dc->res_pool->dp_clock_source;
3244 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3245 unsigned int i;
3246
3247 /*
3248 * Add the logic to extract BOTH power up and power down sequences
3249 * from enable/disable link output and only call edp panel control
3250 * in enable_link_dp and disable_link_dp once.
3251 */
3252 if (link->connector_signal == SIGNAL_TYPE_EDP) {
3253 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
3254 }
3255
3256 /* If the current pixel clock source is not DTO(happens after
3257 * switching from HDMI passive dongle to DP on the same connector),
3258 * switch the pixel clock source to DTO.
3259 */
3260
3261 for (i = 0; i < MAX_PIPES; i++) {
3262 if (pipes[i].stream != NULL &&
3263 pipes[i].stream->link == link) {
3264 if (pipes[i].clock_source != NULL &&
3265 pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
3266 pipes[i].clock_source = dp_cs;
3267 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
3268 pipes[i].stream->timing.pix_clk_100hz;
3269 pipes[i].clock_source->funcs->program_pix_clk(
3270 pipes[i].clock_source,
3271 &pipes[i].stream_res.pix_clk_params,
3272 dc->link_srv->dp_get_encoding_format(link_settings),
3273 &pipes[i].pll_settings);
3274 }
3275 }
3276 }
3277
3278 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
3279 if (dc->clk_mgr->funcs->notify_link_rate_change)
3280 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
3281 }
3282
3283 if (dmcu != NULL && dmcu->funcs->lock_phy)
3284 dmcu->funcs->lock_phy(dmcu);
3285
3286 if (link_hwss->ext.enable_dp_link_output)
3287 link_hwss->ext.enable_dp_link_output(link, link_res, signal,
3288 clock_source, link_settings);
3289
3290 link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
3291
3292 if (dmcu != NULL && dmcu->funcs->unlock_phy)
3293 dmcu->funcs->unlock_phy(dmcu);
3294
3295 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY);
3296 }
3297
dce110_disable_link_output(struct dc_link * link,const struct link_resource * link_res,enum signal_type signal)3298 void dce110_disable_link_output(struct dc_link *link,
3299 const struct link_resource *link_res,
3300 enum signal_type signal)
3301 {
3302 struct dc *dc = link->ctx->dc;
3303 const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
3304 struct dmcu *dmcu = dc->res_pool->dmcu;
3305
3306 if (signal == SIGNAL_TYPE_EDP &&
3307 link->dc->hwss.edp_backlight_control &&
3308 !link->skip_implict_edp_power_control)
3309 link->dc->hwss.edp_backlight_control(link, false);
3310 else if (dmcu != NULL && dmcu->funcs->lock_phy)
3311 dmcu->funcs->lock_phy(dmcu);
3312
3313 link_hwss->disable_link_output(link, link_res, signal);
3314 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
3315 /*
3316 * Add the logic to extract BOTH power up and power down sequences
3317 * from enable/disable link output and only call edp panel control
3318 * in enable_link_dp and disable_link_dp once.
3319 */
3320 if (dmcu != NULL && dmcu->funcs->unlock_phy)
3321 dmcu->funcs->unlock_phy(dmcu);
3322 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
3323 }
3324
3325 static const struct hw_sequencer_funcs dce110_funcs = {
3326 .program_gamut_remap = program_gamut_remap,
3327 .program_output_csc = program_output_csc,
3328 .init_hw = init_hw,
3329 .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
3330 .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
3331 .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
3332 .update_plane_addr = update_plane_addr,
3333 .update_pending_status = dce110_update_pending_status,
3334 .enable_accelerated_mode = dce110_enable_accelerated_mode,
3335 .enable_timing_synchronization = dce110_enable_timing_synchronization,
3336 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
3337 .update_info_frame = dce110_update_info_frame,
3338 .enable_stream = dce110_enable_stream,
3339 .disable_stream = dce110_disable_stream,
3340 .unblank_stream = dce110_unblank_stream,
3341 .blank_stream = dce110_blank_stream,
3342 .enable_audio_stream = dce110_enable_audio_stream,
3343 .disable_audio_stream = dce110_disable_audio_stream,
3344 .disable_plane = dce110_power_down_fe,
3345 .pipe_control_lock = dce_pipe_control_lock,
3346 .interdependent_update_lock = NULL,
3347 .cursor_lock = dce_pipe_control_lock,
3348 .prepare_bandwidth = dce110_prepare_bandwidth,
3349 .optimize_bandwidth = dce110_optimize_bandwidth,
3350 .set_drr = set_drr,
3351 .get_position = get_position,
3352 .set_static_screen_control = set_static_screen_control,
3353 .setup_stereo = NULL,
3354 .set_avmute = dce110_set_avmute,
3355 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
3356 .edp_backlight_control = dce110_edp_backlight_control,
3357 .edp_power_control = dce110_edp_power_control,
3358 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
3359 .set_cursor_position = dce110_set_cursor_position,
3360 .set_cursor_attribute = dce110_set_cursor_attribute,
3361 .set_backlight_level = dce110_set_backlight_level,
3362 .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
3363 .set_pipe = dce110_set_pipe,
3364 .enable_lvds_link_output = dce110_enable_lvds_link_output,
3365 .enable_tmds_link_output = dce110_enable_tmds_link_output,
3366 .enable_dp_link_output = dce110_enable_dp_link_output,
3367 .disable_link_output = dce110_disable_link_output,
3368 };
3369
3370 static const struct hwseq_private_funcs dce110_private_funcs = {
3371 .init_pipes = init_pipes,
3372 .set_input_transfer_func = dce110_set_input_transfer_func,
3373 .set_output_transfer_func = dce110_set_output_transfer_func,
3374 .power_down = dce110_power_down,
3375 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
3376 .enable_display_power_gating = dce110_enable_display_power_gating,
3377 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
3378 .enable_stream_timing = dce110_enable_stream_timing,
3379 .disable_stream_gating = NULL,
3380 .enable_stream_gating = NULL,
3381 .edp_backlight_control = dce110_edp_backlight_control,
3382 };
3383
dce110_hw_sequencer_construct(struct dc * dc)3384 void dce110_hw_sequencer_construct(struct dc *dc)
3385 {
3386 dc->hwss = dce110_funcs;
3387 dc->hwseq->funcs = dce110_private_funcs;
3388 }
3389
3390