Searched hist:e7ecbc057bc5cffb8ad10b6bf7a80684fd426d23 (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/arm/include/asm/hardware/ |
| H A D | cache-uniphier.h | e7ecbc057bc5cffb8ad10b6bf7a80684fd426d23 Fri Oct 02 06:42:19 CEST 2015 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add outer cache support
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| /linux/arch/arm/mm/ |
| H A D | cache-uniphier.c | e7ecbc057bc5cffb8ad10b6bf7a80684fd426d23 Fri Oct 02 06:42:19 CEST 2015 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add outer cache support
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| H A D | Kconfig | diff e7ecbc057bc5cffb8ad10b6bf7a80684fd426d23 Fri Oct 02 06:42:19 CEST 2015 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add outer cache support
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
|
| /linux/ |
| H A D | MAINTAINERS | diff e7ecbc057bc5cffb8ad10b6bf7a80684fd426d23 Fri Oct 02 06:42:19 CEST 2015 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add outer cache support
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
|