Searched hist:e40c7e3cda07099a92ea68d022f3304c14f9659f (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/clk/meson/ |
| H A D | clk-pll.c | diff e40c7e3cda07099a92ea68d022f3304c14f9659f Wed Aug 01 16:00:50 CEST 2018 Jerome Brunet <jbrunet@baylibre.com> clk: meson: clk-pll: add enable bit
Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.
Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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| H A D | axg.c | diff e40c7e3cda07099a92ea68d022f3304c14f9659f Wed Aug 01 16:00:50 CEST 2018 Jerome Brunet <jbrunet@baylibre.com> clk: meson: clk-pll: add enable bit
Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.
Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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| H A D | meson8b.c | diff e40c7e3cda07099a92ea68d022f3304c14f9659f Wed Aug 01 16:00:50 CEST 2018 Jerome Brunet <jbrunet@baylibre.com> clk: meson: clk-pll: add enable bit
Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.
Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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| H A D | gxbb.c | diff e40c7e3cda07099a92ea68d022f3304c14f9659f Wed Aug 01 16:00:50 CEST 2018 Jerome Brunet <jbrunet@baylibre.com> clk: meson: clk-pll: add enable bit
Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.
Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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