Searched hist:d4d8fbcef03f590288b44955d8d51e334627b013 (Results 1 – 3 of 3) sorted by relevance
| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | xlnx,sd-fec.yaml | d4d8fbcef03f590288b44955d8d51e334627b013 Wed Jan 31 18:06:45 CET 2024 Dragan Cvetic <dragan.cvetic@amd.com> dt-bindings: misc: xlnx,sd-fec: convert bindings to yaml
Convert AMD (Xilinx) sd-fec bindings to yaml format, so it can validate
dt-entries as well as any future additions to yaml.
Change in clocks is due to IP is itself configurable and
only the first two clocks are in all combinations. The last
6 clocks can be present in some of them. It means order is
not really fixed and any combination is possible.
Interrupt may or may not be present.
The documentation for sd-fec bindings is now YAML, so update the
MAINTAINERS file.
Update the link to the new yaml file in xilinx_sdfec.rst.
Signed-off-by: Dragan Cvetic <dragan.cvetic@amd.com>
Link: https://lore.kernel.org/r/20240131170650.530079-1-dragan.cvetic@amd.com
Signed-off-by: Rob Herring <robh@kernel.org>
|
| /linux/Documentation/misc-devices/ |
| H A D | xilinx_sdfec.rst | diff d4d8fbcef03f590288b44955d8d51e334627b013 Wed Jan 31 18:06:45 CET 2024 Dragan Cvetic <dragan.cvetic@amd.com> dt-bindings: misc: xlnx,sd-fec: convert bindings to yaml
Convert AMD (Xilinx) sd-fec bindings to yaml format, so it can validate
dt-entries as well as any future additions to yaml.
Change in clocks is due to IP is itself configurable and
only the first two clocks are in all combinations. The last
6 clocks can be present in some of them. It means order is
not really fixed and any combination is possible.
Interrupt may or may not be present.
The documentation for sd-fec bindings is now YAML, so update the
MAINTAINERS file.
Update the link to the new yaml file in xilinx_sdfec.rst.
Signed-off-by: Dragan Cvetic <dragan.cvetic@amd.com>
Link: https://lore.kernel.org/r/20240131170650.530079-1-dragan.cvetic@amd.com
Signed-off-by: Rob Herring <robh@kernel.org>
|
| /linux/ |
| H A D | MAINTAINERS | diff d4d8fbcef03f590288b44955d8d51e334627b013 Wed Jan 31 18:06:45 CET 2024 Dragan Cvetic <dragan.cvetic@amd.com> dt-bindings: misc: xlnx,sd-fec: convert bindings to yaml
Convert AMD (Xilinx) sd-fec bindings to yaml format, so it can validate
dt-entries as well as any future additions to yaml.
Change in clocks is due to IP is itself configurable and
only the first two clocks are in all combinations. The last
6 clocks can be present in some of them. It means order is
not really fixed and any combination is possible.
Interrupt may or may not be present.
The documentation for sd-fec bindings is now YAML, so update the
MAINTAINERS file.
Update the link to the new yaml file in xilinx_sdfec.rst.
Signed-off-by: Dragan Cvetic <dragan.cvetic@amd.com>
Link: https://lore.kernel.org/r/20240131170650.530079-1-dragan.cvetic@amd.com
Signed-off-by: Rob Herring <robh@kernel.org>
|