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| H A D | registers.h | diff b9cc98697d1ca35a86bbb708acc6d93993c28f0f Thu Mar 04 05:21:13 CET 2010 Dan Williams <dan.j.williams@intel.com> ioat3: interrupt coalescing
The hardware automatically disables further interrupts after each event
until rearmed. This allows a delay to be injected between the occurence
of the interrupt and the running of the cleanup routine. The delay is
scaled by the descriptor backlog and then written to the INTRDELAY
register which specifies the number of microseconds to hold off
interrupt delivery after an interrupt event occurs. According to
powertop this reduces the interrupt rate from ~5000 intr/s to ~150
intr/s per without affecting throughput (simple dd to a raid6 array).
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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