1*9ab65affSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2584ec227SDan Williams /* 3584ec227SDan Williams * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. 4584ec227SDan Williams */ 5584ec227SDan Williams #ifndef _IOAT_REGISTERS_H_ 6584ec227SDan Williams #define _IOAT_REGISTERS_H_ 7584ec227SDan Williams 8584ec227SDan Williams #define IOAT_PCI_DMACTRL_OFFSET 0x48 9584ec227SDan Williams #define IOAT_PCI_DMACTRL_DMA_EN 0x00000001 10584ec227SDan Williams #define IOAT_PCI_DMACTRL_MSI_EN 0x00000002 11584ec227SDan Williams 12584ec227SDan Williams #define IOAT_PCI_DEVICE_ID_OFFSET 0x02 13584ec227SDan Williams #define IOAT_PCI_DMAUNCERRSTS_OFFSET 0x148 14a6d52d70SDan Williams #define IOAT_PCI_CHANERR_INT_OFFSET 0x180 15584ec227SDan Williams #define IOAT_PCI_CHANERRMASK_INT_OFFSET 0x184 16584ec227SDan Williams 17584ec227SDan Williams /* MMIO Device Registers */ 18584ec227SDan Williams #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ 19584ec227SDan Williams 20584ec227SDan Williams #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */ 21584ec227SDan Williams #define IOAT_XFERCAP_4KB 12 22584ec227SDan Williams #define IOAT_XFERCAP_8KB 13 23584ec227SDan Williams #define IOAT_XFERCAP_16KB 14 24584ec227SDan Williams #define IOAT_XFERCAP_32KB 15 25584ec227SDan Williams #define IOAT_XFERCAP_32GB 0 26584ec227SDan Williams 27584ec227SDan Williams #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */ 28584ec227SDan Williams #define IOAT_GENCTRL_DEBUG_EN 0x01 29584ec227SDan Williams 30584ec227SDan Williams #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */ 31584ec227SDan Williams #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ 32584ec227SDan Williams #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ 33584ec227SDan Williams #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ 34584ec227SDan Williams #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */ 35584ec227SDan Williams 36584ec227SDan Williams #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ 37584ec227SDan Williams 38584ec227SDan Williams #define IOAT_VER_OFFSET 0x08 /* 8-bit */ 39584ec227SDan Williams #define IOAT_VER_MAJOR_MASK 0xF0 40584ec227SDan Williams #define IOAT_VER_MINOR_MASK 0x0F 41584ec227SDan Williams #define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4) 42584ec227SDan Williams #define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK) 43584ec227SDan Williams 44584ec227SDan Williams #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */ 45584ec227SDan Williams 46584ec227SDan Williams #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */ 47b9cc9869SDan Williams #define IOAT_INTRDELAY_MASK 0x3FFF /* Interrupt Delay Time */ 48584ec227SDan Williams #define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */ 49584ec227SDan Williams 50584ec227SDan Williams #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */ 51584ec227SDan Williams #define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001 522aec048cSDan Williams #define IOAT_DEVICE_MMIO_RESTRICTED 0x0002 532aec048cSDan Williams #define IOAT_DEVICE_MEMORY_BYPASS 0x0004 542aec048cSDan Williams #define IOAT_DEVICE_ADDRESS_REMAPPING 0x0008 552aec048cSDan Williams 562aec048cSDan Williams #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */ 572aec048cSDan Williams #define IOAT_CAP_PAGE_BREAK 0x00000001 582aec048cSDan Williams #define IOAT_CAP_CRC 0x00000002 592aec048cSDan Williams #define IOAT_CAP_SKIP_MARKER 0x00000004 602aec048cSDan Williams #define IOAT_CAP_DCA 0x00000010 612aec048cSDan Williams #define IOAT_CAP_CRC_MOVE 0x00000020 622aec048cSDan Williams #define IOAT_CAP_FILL_BLOCK 0x00000040 632aec048cSDan Williams #define IOAT_CAP_APIC 0x00000080 642aec048cSDan Williams #define IOAT_CAP_XOR 0x00000100 652aec048cSDan Williams #define IOAT_CAP_PQ 0x00000200 6675c6f0abSDave Jiang #define IOAT_CAP_DWBES 0x00002000 677727eaa4SDave Jiang #define IOAT_CAP_RAID16SS 0x00020000 68e0100d40SDave Jiang #define IOAT_CAP_DPS 0x00800000 69e0100d40SDave Jiang 70e0100d40SDave Jiang #define IOAT_PREFETCH_LIMIT_OFFSET 0x4C /* CHWPREFLMT */ 71584ec227SDan Williams 72584ec227SDan Williams #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ 73584ec227SDan Williams 74584ec227SDan Williams /* DMA Channel Registers */ 75584ec227SDan Williams #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */ 76584ec227SDan Williams #define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000 77e61dacaeSDan Williams #define IOAT3_CHANCTRL_COMPL_DCA_EN 0x0200 78584ec227SDan Williams #define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100 79584ec227SDan Williams #define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020 80584ec227SDan Williams #define IOAT_CHANCTRL_ERR_INT_EN 0x0010 81584ec227SDan Williams #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 82584ec227SDan Williams #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 83f6ab95b5SDan Williams #define IOAT_CHANCTRL_INT_REARM 0x0001 84f6ab95b5SDan Williams #define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\ 853f09ede4SDave Jiang IOAT_CHANCTRL_ERR_INT_EN |\ 863f09ede4SDave Jiang IOAT_CHANCTRL_ERR_COMPLETION_EN |\ 876f82b83bSDan Williams IOAT_CHANCTRL_ANY_ERR_ABORT_EN) 88584ec227SDan Williams 89584ec227SDan Williams #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ 90584ec227SDan Williams #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ 91584ec227SDan Williams #define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */ 92584ec227SDan Williams 93d3cd63f9SDave Jiang #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */ 944fb9b9e8SDan Williams #define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL) 954fb9b9e8SDan Williams #define IOAT_CHANSTS_SOFT_ERR 0x10ULL 964fb9b9e8SDan Williams #define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL 9709c8a5b8SDan Williams #define IOAT_CHANSTS_STATUS 0x7ULL 9809c8a5b8SDan Williams #define IOAT_CHANSTS_ACTIVE 0x0 9909c8a5b8SDan Williams #define IOAT_CHANSTS_DONE 0x1 10009c8a5b8SDan Williams #define IOAT_CHANSTS_SUSPENDED 0x2 10109c8a5b8SDan Williams #define IOAT_CHANSTS_HALTED 0x3 102584ec227SDan Williams 103584ec227SDan Williams 104584ec227SDan Williams 105584ec227SDan Williams #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */ 106584ec227SDan Williams 107584ec227SDan Williams #define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */ 108584ec227SDan Williams #define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000 109584ec227SDan Williams #define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */ 110584ec227SDan Williams 111584ec227SDan Williams /* CB DCA Memory Space Registers */ 112584ec227SDan Williams #define IOAT_DCAOFFSET_OFFSET 0x14 113584ec227SDan Williams /* CB_BAR + IOAT_DCAOFFSET value */ 114584ec227SDan Williams #define IOAT_DCA_VER_OFFSET 0x00 115584ec227SDan Williams #define IOAT_DCA_VER_MAJOR_MASK 0xF0 116584ec227SDan Williams #define IOAT_DCA_VER_MINOR_MASK 0x0F 117584ec227SDan Williams 118584ec227SDan Williams #define IOAT_DCA_COMP_OFFSET 0x02 119584ec227SDan Williams #define IOAT_DCA_COMP_V1 0x1 120584ec227SDan Williams 121584ec227SDan Williams #define IOAT_FSB_CAPABILITY_OFFSET 0x04 122584ec227SDan Williams #define IOAT_FSB_CAPABILITY_PREFETCH 0x1 123584ec227SDan Williams 124584ec227SDan Williams #define IOAT_PCI_CAPABILITY_OFFSET 0x06 125584ec227SDan Williams #define IOAT_PCI_CAPABILITY_MEMWR 0x1 126584ec227SDan Williams 127584ec227SDan Williams #define IOAT_FSB_CAP_ENABLE_OFFSET 0x08 128584ec227SDan Williams #define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1 129584ec227SDan Williams 130584ec227SDan Williams #define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A 131584ec227SDan Williams #define IOAT_PCI_CAP_ENABLE_MEMWR 0x1 132584ec227SDan Williams 133584ec227SDan Williams #define IOAT_APICID_TAG_MAP_OFFSET 0x0C 134584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG0 0x0000000F 135584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0 136584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG1 0x000000F0 137584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4 138584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG2 0x00000F00 139584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8 140584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG3 0x0000F000 141584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12 142584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG4 0x000F0000 143584ec227SDan Williams #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16 144584ec227SDan Williams #define IOAT_APICID_TAG_CB2_VALID 0x8080808080 145584ec227SDan Williams 146584ec227SDan Williams #define IOAT_DCA_GREQID_OFFSET 0x10 147584ec227SDan Williams #define IOAT_DCA_GREQID_SIZE 0x04 148584ec227SDan Williams #define IOAT_DCA_GREQID_MASK 0xFFFF 149584ec227SDan Williams #define IOAT_DCA_GREQID_IGNOREFUN 0x10000000 150584ec227SDan Williams #define IOAT_DCA_GREQID_VALID 0x20000000 151584ec227SDan Williams #define IOAT_DCA_GREQID_LASTID 0x80000000 152584ec227SDan Williams 153584ec227SDan Williams #define IOAT3_CSI_CAPABILITY_OFFSET 0x08 154584ec227SDan Williams #define IOAT3_CSI_CAPABILITY_PREFETCH 0x1 155584ec227SDan Williams 156584ec227SDan Williams #define IOAT3_PCI_CAPABILITY_OFFSET 0x0A 157584ec227SDan Williams #define IOAT3_PCI_CAPABILITY_MEMWR 0x1 158584ec227SDan Williams 159584ec227SDan Williams #define IOAT3_CSI_CONTROL_OFFSET 0x0C 160584ec227SDan Williams #define IOAT3_CSI_CONTROL_PREFETCH 0x1 161584ec227SDan Williams 162584ec227SDan Williams #define IOAT3_PCI_CONTROL_OFFSET 0x0E 163584ec227SDan Williams #define IOAT3_PCI_CONTROL_MEMWR 0x1 164584ec227SDan Williams 165584ec227SDan Williams #define IOAT3_APICID_TAG_MAP_OFFSET 0x10 166584ec227SDan Williams #define IOAT3_APICID_TAG_MAP_OFFSET_LOW 0x10 167584ec227SDan Williams #define IOAT3_APICID_TAG_MAP_OFFSET_HIGH 0x14 168584ec227SDan Williams 169584ec227SDan Williams #define IOAT3_DCA_GREQID_OFFSET 0x02 170584ec227SDan Williams 171584ec227SDan Williams #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */ 172584ec227SDan Williams #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */ 173584ec227SDan Williams #define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 174584ec227SDan Williams ? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET) 175584ec227SDan Williams #define IOAT1_CHAINADDR_OFFSET_LOW 0x0C 176584ec227SDan Williams #define IOAT2_CHAINADDR_OFFSET_LOW 0x10 177584ec227SDan Williams #define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \ 178584ec227SDan Williams ? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW) 179584ec227SDan Williams #define IOAT1_CHAINADDR_OFFSET_HIGH 0x10 180584ec227SDan Williams #define IOAT2_CHAINADDR_OFFSET_HIGH 0x14 181584ec227SDan Williams #define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \ 182584ec227SDan Williams ? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH) 183584ec227SDan Williams 184584ec227SDan Williams #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */ 185584ec227SDan Williams #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */ 186584ec227SDan Williams #define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \ 187584ec227SDan Williams ? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET) 188584ec227SDan Williams #define IOAT_CHANCMD_RESET 0x20 189584ec227SDan Williams #define IOAT_CHANCMD_RESUME 0x10 190584ec227SDan Williams #define IOAT_CHANCMD_ABORT 0x08 191584ec227SDan Williams #define IOAT_CHANCMD_SUSPEND 0x04 192584ec227SDan Williams #define IOAT_CHANCMD_APPEND 0x02 193584ec227SDan Williams #define IOAT_CHANCMD_START 0x01 194584ec227SDan Williams 195584ec227SDan Williams #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */ 196584ec227SDan Williams #define IOAT_CHANCMP_OFFSET_LOW 0x18 197584ec227SDan Williams #define IOAT_CHANCMP_OFFSET_HIGH 0x1C 198584ec227SDan Williams 199584ec227SDan Williams #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */ 200584ec227SDan Williams #define IOAT_CDAR_OFFSET_LOW 0x20 201584ec227SDan Williams #define IOAT_CDAR_OFFSET_HIGH 0x24 202584ec227SDan Williams 203584ec227SDan Williams #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */ 20409c8a5b8SDan Williams #define IOAT_CHANERR_SRC_ADDR_ERR 0x0001 20509c8a5b8SDan Williams #define IOAT_CHANERR_DEST_ADDR_ERR 0x0002 20609c8a5b8SDan Williams #define IOAT_CHANERR_NEXT_ADDR_ERR 0x0004 20709c8a5b8SDan Williams #define IOAT_CHANERR_NEXT_DESC_ALIGN_ERR 0x0008 208584ec227SDan Williams #define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010 209584ec227SDan Williams #define IOAT_CHANERR_CHANCMD_ERR 0x0020 210584ec227SDan Williams #define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040 211584ec227SDan Williams #define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080 212584ec227SDan Williams #define IOAT_CHANERR_READ_DATA_ERR 0x0100 213584ec227SDan Williams #define IOAT_CHANERR_WRITE_DATA_ERR 0x0200 21409c8a5b8SDan Williams #define IOAT_CHANERR_CONTROL_ERR 0x0400 21509c8a5b8SDan Williams #define IOAT_CHANERR_LENGTH_ERR 0x0800 216584ec227SDan Williams #define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000 217584ec227SDan Williams #define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000 218584ec227SDan Williams #define IOAT_CHANERR_SOFT_ERR 0x4000 219584ec227SDan Williams #define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000 2202aec048cSDan Williams #define IOAT_CHANERR_XOR_P_OR_CRC_ERR 0x10000 2212aec048cSDan Williams #define IOAT_CHANERR_XOR_Q_ERR 0x20000 2222aec048cSDan Williams #define IOAT_CHANERR_DESCRIPTOR_COUNT_ERR 0x40000 223584ec227SDan Williams 224b094ad3bSDan Williams #define IOAT_CHANERR_HANDLE_MASK (IOAT_CHANERR_XOR_P_OR_CRC_ERR | IOAT_CHANERR_XOR_Q_ERR) 2259546d4cdSDave Jiang #define IOAT_CHANERR_RECOVER_MASK (IOAT_CHANERR_READ_DATA_ERR | \ 2269546d4cdSDave Jiang IOAT_CHANERR_WRITE_DATA_ERR) 227b094ad3bSDan Williams 228584ec227SDan Williams #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ 229584ec227SDan Williams 230e0100d40SDave Jiang #define IOAT_CHAN_DRSCTL_OFFSET 0xB6 231e0100d40SDave Jiang #define IOAT_CHAN_DRSZ_4KB 0x0000 232e0100d40SDave Jiang #define IOAT_CHAN_DRSZ_8KB 0x0001 233e0100d40SDave Jiang #define IOAT_CHAN_DRSZ_2MB 0x0009 234e0100d40SDave Jiang #define IOAT_CHAN_DRS_EN 0x0100 235e0100d40SDave Jiang #define IOAT_CHAN_DRS_AUTOWRAP 0x0200 236e0100d40SDave Jiang 237528314b5SDave Jiang #define IOAT_CHAN_LTR_SWSEL_OFFSET 0xBC 238528314b5SDave Jiang #define IOAT_CHAN_LTR_SWSEL_ACTIVE 0x0 239528314b5SDave Jiang #define IOAT_CHAN_LTR_SWSEL_IDLE 0x1 240528314b5SDave Jiang 241528314b5SDave Jiang #define IOAT_CHAN_LTR_ACTIVE_OFFSET 0xC0 242528314b5SDave Jiang #define IOAT_CHAN_LTR_ACTIVE_SNVAL 0x0000 /* 0 us */ 243528314b5SDave Jiang #define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE 0x0800 /* 1us scale */ 244528314b5SDave Jiang #define IOAT_CHAN_LTR_ACTIVE_SNREQMNT 0x8000 /* snoop req enable */ 245528314b5SDave Jiang 246528314b5SDave Jiang #define IOAT_CHAN_LTR_IDLE_OFFSET 0xC4 247528314b5SDave Jiang #define IOAT_CHAN_LTR_IDLE_SNVAL 0x0258 /* 600 us */ 248528314b5SDave Jiang #define IOAT_CHAN_LTR_IDLE_SNLATSCALE 0x0800 /* 1us scale */ 249528314b5SDave Jiang #define IOAT_CHAN_LTR_IDLE_SNREQMNT 0x8000 /* snoop req enable */ 250528314b5SDave Jiang 251584ec227SDan Williams #endif /* _IOAT_REGISTERS_H_ */ 252