Searched hist:b6ec400aa153b27e056b2dfc5e830b724c053a04 (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/clk/meson/ |
| H A D | clk-pll.h | diff b6ec400aa153b27e056b2dfc5e830b724c053a04 Tue May 23 15:53:47 CEST 2023 Dmitry Rokosov <ddrokosov@sberdevices.ru> clk: meson: introduce new pll power-on sequence for A1 SoC family
Modern meson PLL IPs are a little bit different from early known PLLs.
The main difference is located in the init/enable/disable sequences; the
rate logic is the same.
In A1 PLL, the PLL enable sequence is different, so add new optional pll
reg bits and use the new power-on sequence to enable the PLL:
1. enable the pll, delay for 10us
2. enable the pll self-adaption current module, delay for 40us
3. enable the lock detect module
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230523135351.19133-3-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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| H A D | clk-pll.c | diff b6ec400aa153b27e056b2dfc5e830b724c053a04 Tue May 23 15:53:47 CEST 2023 Dmitry Rokosov <ddrokosov@sberdevices.ru> clk: meson: introduce new pll power-on sequence for A1 SoC family
Modern meson PLL IPs are a little bit different from early known PLLs.
The main difference is located in the init/enable/disable sequences; the
rate logic is the same.
In A1 PLL, the PLL enable sequence is different, so add new optional pll
reg bits and use the new power-on sequence to enable the PLL:
1. enable the pll, delay for 10us
2. enable the pll self-adaption current module, delay for 40us
3. enable the lock detect module
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230523135351.19133-3-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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