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/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
H A Dbase.cb62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
H A Dgp102.cb62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
H A DKbuildb62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
H A Dpriv.hb62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dgk104.cdiff b62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/linux/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dsec2.hb62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/linux/drivers/gpu/drm/nouveau/nvkm/engine/
H A DKbuilddiff b62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/linux/drivers/gpu/drm/nouveau/nvkm/core/
H A Dsubdev.cdiff b62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/linux/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dpriv.hdiff b62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
H A Dbase.cdiff b62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
/linux/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Ddevice.hdiff b62880f7966781eb0b3b1e50f63d6aac362476d3 Thu Feb 23 10:41:41 CET 2017 Alexandre Courbot <acourbot@nvidia.com> drm/nouveau/core: add SEC2 engine

SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons
unknown). Even though it shares the same address range as SEC, its usage
is quite different and this justifies a new engine. Add this engine and
make TOP use it all post-TOP devices should use this implementation and
not the older SEC.

Also quickly add the short gp102 implementation which will be used for
falcon booting purposes.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>