Searched hist:a563f7598198b8389e00451ef6f3f1c12efbfb99 (Results 1 – 2 of 2) sorted by relevance
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| H A D | pgtable-hwdef.h | diff a563f7598198b8389e00451ef6f3f1c12efbfb99 Mon Apr 04 12:43:15 CEST 2016 Suzuki K Poulose <suzuki.poulose@arm.com> arm64: Reuse TCR field definitions for EL1 and EL2
TCR_EL1, TCR_EL2 and VTCR_EL2, all share some field positions
(TG0, ORGN0, IRGN0 and SH0) and their corresponding value definitions.
This patch makes the TCR_EL1 definitions reusable and uses them for TCR_EL2
and VTCR_EL2 fields.
This also fixes a bug where we assume TG0 in {V}TCR_EL2 is 1bit field.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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| H A D | kvm_arm.h | diff a563f7598198b8389e00451ef6f3f1c12efbfb99 Mon Apr 04 12:43:15 CEST 2016 Suzuki K Poulose <suzuki.poulose@arm.com> arm64: Reuse TCR field definitions for EL1 and EL2
TCR_EL1, TCR_EL2 and VTCR_EL2, all share some field positions
(TG0, ORGN0, IRGN0 and SH0) and their corresponding value definitions.
This patch makes the TCR_EL1 definitions reusable and uses them for TCR_EL2
and VTCR_EL2 fields.
This also fixes a bug where we assume TG0 in {V}TCR_EL2 is 1bit field.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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