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/linux/include/dt-bindings/soc/
H A Dqe-fsl,tsa.ha0bbe77fafbc7e5eb41fbf3dc5cdb3608d8778a3 Thu Aug 08 09:11:00 CEST 2024 Herve Codina <herve.codina@bootlin.com> dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) TSA controller

Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.

This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-8-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-tsa.yamla0bbe77fafbc7e5eb41fbf3dc5cdb3608d8778a3 Thu Aug 08 09:11:00 CEST 2024 Herve Codina <herve.codina@bootlin.com> dt-bindings: soc: fsl: cpm_qe: Add QUICC Engine (QE) TSA controller

Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.

This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-8-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>