Searched hist:"70768 ebaa5872e11f68d71761bb9fa1546cb451e" (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/mips/include/asm/mach-loongson64/ |
| H A D | cpucfg-emul.h | diff 70768ebaa5872e11f68d71761bb9fa1546cb451e Sat May 30 09:32:41 CEST 2020 WANG Xuerui <git@xen0n.name> MIPS: Loongson64: Guard against future cores without CPUCFG
Previously it was thought that all future Loongson cores would come with
native CPUCFG. From new information shared by Huacai this is definitely
not true (maybe some future 2K cores, for example), so collisions at
PRID_REV level are inevitable. The CPU model matching needs to take
PRID_IMP into consideration.
The emulation logic needs to be disabled for those future cores as well,
as we cannot possibly encode their non-discoverable features right now.
Reported-by: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
|
| /linux/arch/mips/loongson64/ |
| H A D | cpucfg-emul.c | diff 70768ebaa5872e11f68d71761bb9fa1546cb451e Sat May 30 09:32:41 CEST 2020 WANG Xuerui <git@xen0n.name> MIPS: Loongson64: Guard against future cores without CPUCFG
Previously it was thought that all future Loongson cores would come with
native CPUCFG. From new information shared by Huacai this is definitely
not true (maybe some future 2K cores, for example), so collisions at
PRID_REV level are inevitable. The CPU model matching needs to take
PRID_IMP into consideration.
The emulation logic needs to be disabled for those future cores as well,
as we cannot possibly encode their non-discoverable features right now.
Reported-by: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
|
| /linux/arch/mips/kernel/ |
| H A D | traps.c | diff 70768ebaa5872e11f68d71761bb9fa1546cb451e Sat May 30 09:32:41 CEST 2020 WANG Xuerui <git@xen0n.name> MIPS: Loongson64: Guard against future cores without CPUCFG
Previously it was thought that all future Loongson cores would come with
native CPUCFG. From new information shared by Huacai this is definitely
not true (maybe some future 2K cores, for example), so collisions at
PRID_REV level are inevitable. The CPU model matching needs to take
PRID_IMP into consideration.
The emulation logic needs to be disabled for those future cores as well,
as we cannot possibly encode their non-discoverable features right now.
Reported-by: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
|