Searched hist:"706 cffc1b912342668e621526c860fb093dfc2d5" (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/irqchip/ |
| H A D | irq-sni-exiu.c | 706cffc1b912342668e621526c860fb093dfc2d5 Mon Nov 06 19:34:37 CET 2017 Ard Biesheuvel <ard.biesheuvel@linaro.org> irqchip/exiu: Add support for Socionext Synquacer EXIU controller
The Socionext Synquacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.
The EXIU has per-interrupt level/edge and polarity controls, and
mask bits that keep the outgoing lines de-asserted, even though
the controller may still latch interrupt conditions that occur
while the line is masked.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
|
| H A D | Makefile | diff 706cffc1b912342668e621526c860fb093dfc2d5 Mon Nov 06 19:34:37 CET 2017 Ard Biesheuvel <ard.biesheuvel@linaro.org> irqchip/exiu: Add support for Socionext Synquacer EXIU controller
The Socionext Synquacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.
The EXIU has per-interrupt level/edge and polarity controls, and
mask bits that keep the outgoing lines de-asserted, even though
the controller may still latch interrupt conditions that occur
while the line is masked.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
|
| /linux/arch/arm64/ |
| H A D | Kconfig.platforms | diff 706cffc1b912342668e621526c860fb093dfc2d5 Mon Nov 06 19:34:37 CET 2017 Ard Biesheuvel <ard.biesheuvel@linaro.org> irqchip/exiu: Add support for Socionext Synquacer EXIU controller
The Socionext Synquacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.
The EXIU has per-interrupt level/edge and polarity controls, and
mask bits that keep the outgoing lines de-asserted, even though
the controller may still latch interrupt conditions that occur
while the line is masked.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
|