Searched hist:"492 c1ae2f27c327ef8d0f2019cac66408a41d808" (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_display_power.h | diff 492c1ae2f27c327ef8d0f2019cac66408a41d808 Tue Feb 22 17:51:30 CET 2022 Imre Deak <imre.deak@intel.com> drm/i915: Fix the VDSC_PW2 power domain enum value
The POWER_DOMAIN_TRANSCODER() macro depends on the
POWER_DOMAIN_TRANSCODER_A/B .. DSI_A/C enum values to be consecutive,
move POWER_DOMAIN_TRANSCODER_VDSC_PW2 after these to ensure this. The
wrong order didn't cause a problem, since the DSI_A/C domains are in
always-on power wells on all relevant platforms. The same power well
ends up being enabled/disabled when the VDSC_PW2 domain is selected
incorrectly.
While at it add a code comment about enum values that need to stay
consecutive.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220222165137.1004194-2-imre.deak@intel.com
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| H A D | intel_display_power.c | diff 492c1ae2f27c327ef8d0f2019cac66408a41d808 Tue Feb 22 17:51:30 CET 2022 Imre Deak <imre.deak@intel.com> drm/i915: Fix the VDSC_PW2 power domain enum value
The POWER_DOMAIN_TRANSCODER() macro depends on the
POWER_DOMAIN_TRANSCODER_A/B .. DSI_A/C enum values to be consecutive,
move POWER_DOMAIN_TRANSCODER_VDSC_PW2 after these to ensure this. The
wrong order didn't cause a problem, since the DSI_A/C domains are in
always-on power wells on all relevant platforms. The same power well
ends up being enabled/disabled when the VDSC_PW2 domain is selected
incorrectly.
While at it add a code comment about enum values that need to stay
consecutive.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220222165137.1004194-2-imre.deak@intel.com
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