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| /linux/drivers/clk/meson/ |
| H A D | clk-pll.h | diff 39b8500283b45252e2f9ad9d60992f2c0d3a1659 Thu Mar 07 15:14:53 CET 2019 Neil Armstrong <narmstrong@baylibre.com> clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
The Meson G12A PCIE PLL is fined tuned to deliver a very precise
100MHz reference clock for the PCIe Analog PHY, and thus requires
a strict register sequence to enable the PLL.
To simplify, use the _init() op to enable the PLL and keep
the other ops except set_rate since the rate is fixed.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190307141455.23879-2-narmstrong@baylibre.com
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| H A D | clk-pll.c | diff 39b8500283b45252e2f9ad9d60992f2c0d3a1659 Thu Mar 07 15:14:53 CET 2019 Neil Armstrong <narmstrong@baylibre.com> clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
The Meson G12A PCIE PLL is fined tuned to deliver a very precise
100MHz reference clock for the PCIe Analog PHY, and thus requires
a strict register sequence to enable the PLL.
To simplify, use the _init() op to enable the PLL and keep
the other ops except set_rate since the rate is fixed.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190307141455.23879-2-narmstrong@baylibre.com
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