Searched hist:"206 a2a73a62d37c8b8f6ddd3180c202b2e7298ab" (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/arm64/include/asm/ |
| H A D | pgtable-hwdef.h | diff 206a2a73a62d37c8b8f6ddd3180c202b2e7298ab Tue May 06 15:02:27 CEST 2014 Steve Capper <steve.capper@linaro.org> arm64: mm: Create gigabyte kernel logical mappings where possible
We have the capability to map 1GB level 1 blocks when using a 4K
granule.
This patch adjusts the create_mapping logic s.t. when mapping physical
memory on boot, we attempt to use a 1GB block if both the VA and PA
start and end are 1GB aligned. This both reduces the levels of lookup
required to resolve a kernel logical address, as well as reduces TLB
pressure on cores that support 1GB TLB entries.
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Tested-by: Jungseok Lee <jays.lee@samsung.com>
[catalin.marinas@arm.com: s/prot_sect_kernel/PROT_SECT_NORMAL_EXEC/]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
| /linux/arch/arm64/mm/ |
| H A D | mmu.c | diff 206a2a73a62d37c8b8f6ddd3180c202b2e7298ab Tue May 06 15:02:27 CEST 2014 Steve Capper <steve.capper@linaro.org> arm64: mm: Create gigabyte kernel logical mappings where possible
We have the capability to map 1GB level 1 blocks when using a 4K
granule.
This patch adjusts the create_mapping logic s.t. when mapping physical
memory on boot, we attempt to use a 1GB block if both the VA and PA
start and end are 1GB aligned. This both reduces the levels of lookup
required to resolve a kernel logical address, as well as reduces TLB
pressure on cores that support 1GB TLB entries.
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Tested-by: Jungseok Lee <jays.lee@samsung.com>
[catalin.marinas@arm.com: s/prot_sect_kernel/PROT_SECT_NORMAL_EXEC/]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|