Searched hist:"1 fc3b37f34f69ee3fd61ca624fc005fb0bfe3984" (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/media/platform/cadence/ |
| H A D | Makefile | 1fc3b37f34f69ee3fd61ca624fc005fb0bfe3984 Fri May 04 16:08:08 CEST 2018 Maxime Ripard <maxime.ripard@bootlin.com> media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver
The Cadence CSI-2 RX Controller is an hardware block meant to be used as a
bridge between a CSI-2 bus and pixel grabbers.
It supports operating with internal or external D-PHY, with up to 4 lanes,
or without any D-PHY. The current code only supports the latter case.
It also support dynamic mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
|
| H A D | Kconfig | 1fc3b37f34f69ee3fd61ca624fc005fb0bfe3984 Fri May 04 16:08:08 CEST 2018 Maxime Ripard <maxime.ripard@bootlin.com> media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver
The Cadence CSI-2 RX Controller is an hardware block meant to be used as a
bridge between a CSI-2 bus and pixel grabbers.
It supports operating with internal or external D-PHY, with up to 4 lanes,
or without any D-PHY. The current code only supports the latter case.
It also support dynamic mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
|
| /linux/drivers/media/platform/ |
| H A D | Makefile | diff 1fc3b37f34f69ee3fd61ca624fc005fb0bfe3984 Fri May 04 16:08:08 CEST 2018 Maxime Ripard <maxime.ripard@bootlin.com> media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver
The Cadence CSI-2 RX Controller is an hardware block meant to be used as a
bridge between a CSI-2 bus and pixel grabbers.
It supports operating with internal or external D-PHY, with up to 4 lanes,
or without any D-PHY. The current code only supports the latter case.
It also support dynamic mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
|
| H A D | Kconfig | diff 1fc3b37f34f69ee3fd61ca624fc005fb0bfe3984 Fri May 04 16:08:08 CEST 2018 Maxime Ripard <maxime.ripard@bootlin.com> media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver
The Cadence CSI-2 RX Controller is an hardware block meant to be used as a
bridge between a CSI-2 bus and pixel grabbers.
It supports operating with internal or external D-PHY, with up to 4 lanes,
or without any D-PHY. The current code only supports the latter case.
It also support dynamic mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
|
| /linux/ |
| H A D | MAINTAINERS | diff 1fc3b37f34f69ee3fd61ca624fc005fb0bfe3984 Fri May 04 16:08:08 CEST 2018 Maxime Ripard <maxime.ripard@bootlin.com> media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver
The Cadence CSI-2 RX Controller is an hardware block meant to be used as a
bridge between a CSI-2 bus and pixel grabbers.
It supports operating with internal or external D-PHY, with up to 4 lanes,
or without any D-PHY. The current code only supports the latter case.
It also support dynamic mapping of the CSI-2 virtual channels to the
associated pixel grabbers, but that isn't allowed at the moment either.
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
|