Searched hist:"178 e9fc47aaec1b8952b553444e94802d7570599" (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/riscv/include/asm/ |
| H A D | Kbuild | diff 178e9fc47aaec1b8952b553444e94802d7570599 Fri Apr 20 01:27:49 CEST 2018 Alan Kao <alankao@andestech.com> perf: riscv: preliminary RISC-V support
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu <nickhu@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Signed-off-by: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
|
| /linux/arch/riscv/kernel/ |
| H A D | Makefile | diff 178e9fc47aaec1b8952b553444e94802d7570599 Fri Apr 20 01:27:49 CEST 2018 Alan Kao <alankao@andestech.com> perf: riscv: preliminary RISC-V support
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu <nickhu@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Signed-off-by: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
|
| /linux/arch/riscv/ |
| H A D | Kconfig | diff 178e9fc47aaec1b8952b553444e94802d7570599 Fri Apr 20 01:27:49 CEST 2018 Alan Kao <alankao@andestech.com> perf: riscv: preliminary RISC-V support
This patch provide a basic PMU, riscv_base_pmu, which supports two
general hardware event, instructions and cycles. Furthermore, this
PMU serves as a reference implementation to ease the portings in
the future.
riscv_base_pmu should be able to run on any RISC-V machine that
conforms to the Priv-Spec. Note that the latest qemu model hasn't
fully support a proper behavior of Priv-Spec 1.10 yet, but work
around should be easy with very small fixes. Please check
https://github.com/riscv/riscv-qemu/pull/115 for future updates.
Cc: Nick Hu <nickhu@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Signed-off-by: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
|