Searched +full:zynqmp +full:- +full:dpsub +full:- +full:1 (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx ZynqMP DisplayPort Subsystem10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)14 +------------------------------------------------------------+15 +--------+ | +----------------+ +-----------+ |16 | DPDMA | --->| | --> | Video | Video +-------------+ |17 | 4x vid | | | | | Rendering | -+--> | | | +------+[all …]
1 // SPDX-License-Identifier: GPL-2.03 * ZynqMP DisplayPort Subsystem - KMS API5 * Copyright (C) 2017 - 2021 Xilinx, Inc.8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>47 return container_of(drm, struct zynqmp_dpsub_drm, dev)->dpsub; in to_zynqmp_dpsub()50 /* -----------------------------------------------------------------------------61 if (!new_plane_state->crtc) in zynqmp_dpsub_plane_atomic_check()64 crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); in zynqmp_dpsub_plane_atomic_check()80 struct zynqmp_dpsub *dpsub = to_zynqmp_dpsub(plane->dev); in zynqmp_dpsub_plane_atomic_disable() local[all …]
1 // SPDX-License-Identifier: GPL-2.03 * ZynqMP Display Controller Driver5 * Copyright (C) 2017 - 2020 Xilinx, Inc.8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>19 #include <linux/dma-mapping.h>21 #include <linux/media-bus-format.h>34 * --------36 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video39 * +------------------------------------------------------------+[all …]
1 // SPDX-License-Identifier: GPL-2.03 * ZynqMP DisplayPort Driver5 * Copyright (C) 2017 - 2020 Xilinx, Inc.8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>27 #include <linux/media-bus-format.h>61 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2 BIT(1)98 #define ZYNQMP_DP_CORE_ID_DIRECTION GENMASK(1)111 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST BIT(1)118 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER BIT(1)[all …]