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Searched +full:zynq +full:- +full:spi +full:- +full:r1p6 (Results 1 – 3 of 3) sorted by relevance

/linux/Documentation/devicetree/bindings/spi/
H A Dspi-cadence.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SPI controller
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - enum:
19 - xlnx,zynq-spi-r1p6
20 - items:
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 u-boot {
13 compatible = "u-boot,config";
14 bootscr-address = /bits/ 64 <0x3000000>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux/drivers/spi/
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cadence SPI controller driver (host and target mode)
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
22 #include <linux/spi/spi.h>
25 #define CDNS_SPI_NAME "cdns-spi"
42 * SPI Configuration Register bit Masks
45 * of the SPI controller
63 * SPI Configuration Register - Baud rate and target select
77 * SPI Interrupt Registers bit Masks
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