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Searched +full:xtal +full:- +full:load +full:- +full:pf (Results 1 – 6 of 6) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
24 - ti,cdce925
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/linux/include/linux/mfd/
H A Dsi476x-platform.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/media/si476x-platform.h -- Platform data specific definitions
185 * @xcload: Selects the amount of additional on-chip capacitance to
188 * additional load capacitance presented to the xtal. The
189 * minimum step size is 0.277 pF. Recommended value is 0x28
191 * (0–16.33 pF)
197 * SI476X_BOOTLOADER - Boot loader
198 * SI476X_FM_RECEIVER - FM receiver
199 * SI476X_AM_RECEIVER - AM receiver
200 * SI476X_WB_RECEIVER - Weatherband receiver
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/linux/drivers/clk/
H A Dclk-versaclock5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * - Use spread spectrum
11 * - Use integer divider in FOD if applicable
15 #include <linux/clk-provider.h>
26 #include <dt-bindings/clock/versaclock.h>
31 /* Factory-reserved register block */
139 /* chip has built-in oscilator */
206 /* Factory reserved regs, make them read-only */ in vc5_regmap_is_writeable()
210 /* Factory reserved regs, make them read-only */ in vc5_regmap_is_writeable()
226 * VersaClock5 input multiplexer between XTAL and CLKIN divider
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H A Dclk-cdce925.c5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
14 #include <linux/clk-provider.h>
54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
92 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
146 data->m = 0; /* Bypass mode */ in cdce925_pll_set_rate()
147 data->n = 0; in cdce925_pll_set_rate()
154 return -EINVAL; in cdce925_pll_set_rate()
160 return -EINVAL; in cdce925_pll_set_rate()
163 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); in cdce925_pll_set_rate()
168 /* calculate p = max(0, 4 - int(log2 (n/m))) */
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/linux/drivers/media/dvb-frontends/
H A Dhelene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Sony HELENE DVB-S/S2 DVB-T/T2 DVB-C/C2 ISDB-T/S tuner driver (CXD2858ER)
34 enum helene_xtal xtal; member
54 /**< System-M (Japan) (IF: Fp=5.75MHz in default) */
56 /**< System-M (US) (IF: Fp=5.75MHz in default) */
58 /**< System-M (Korea) (IF: Fp=5.9MHz in default) */
60 /**< System-B/G (IF: Fp=7.3MHz in default) */
62 /**< System-I (IF: Fp=7.85MHz in default) */
64 /**< System-D/K (IF: Fp=7.85MHz in default) */
66 /**< System-L (IF: Fp=7.85MHz in default) */
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/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
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