Lines Matching +full:xtal +full:- +full:load +full:- +full:pf
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
196 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
203 * De-interlacer Mode
205 * 0 Normal Un-Shuffled Frame
210 * 11: Un-used
211 * 10: down-sample to 1/4
212 * 01: down-sample to 1/2
213 * 00: down-sample disabled
218 * 11: Un-used
219 * 10: down-sample to 1/4
220 * 01: down-sample to 1/2
221 * 00: down-sample disabled
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
422 * Swap byte order of VLC stream in d-word.
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
699 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
781 * 0 no 5pF (default)
782 * 1 5pF added
804 * Become valid after sync to the xtal clock domain. This bit is set only if
805 * LOAD register bit is also set to 1.
811 * LOAD register bit is also set to 1.
815 * Issue SPLL (108 MHz) configuration load from Async host interface / PCI
817 * the LOAD register bit is also set to 1.
821 * Set this bit to latch the SRST, SYSPLL_CFG, SPLL_CFG setting into the xtal
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
848 * 1 High level or pos-edge is assertion
849 * 0 Low level or neg-edge is assertion
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
992 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1068 * 1 DDR self-test mode
1072 * 0 DDR self-test single read/write
1073 * 1 DDR self-test burst read/write
1077 * 0 DDR self-test write command
1078 * 1 DDR self-test read command
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1312 * Every channel of preview and audio have ping-pong buffers in system memory,
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1411 /* Length of 32-bit data burst */
1444 /* 0x84000 - 0x87ffc */
1454 /* Read-only register */
1469 * 1 Sub-carrier PLL is locked to the incoming video source.
1470 * 0 Sub-carrier PLL is not locked.
1497 /* VCR signal indicator. Read-only. */
1499 /* Weak signal indicator 2. Read-only. */
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1505 * 0 = Non-standard signal
1506 * Read-only
1510 * 1 = Non-interlaced signal
1512 * Read-only
1559 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1598 * These bits control the brightness. They have value of -128 to 127 in 2's
1624 /* Read-only */
1627 /* Macrovision color stripe detection may be un-reliable */
1641 /* Read-only */
1645 * Read-only.
1687 * process. This bit is a self-clearing bit
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1746 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1749 * 2 u-Law output
1750 * 3 A-Law output
1774 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1820 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1842 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1847 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1850 * 2 u-Law input
1851 * 3 A-Law input
1882 * Interrupt status register from the front-end. Write "1" to each bit to clear
2003 * Define the threshold of sub-cell number for motion detection.
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005 * 1 Motion is detected if 2 sub-cells have motion
2006 * 2 Motion is detected if 3 sub-cells have motion
2007 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)