Searched +full:xps +full:- +full:timebase +full:- +full:wdt +full:- +full:1 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause3 ---4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>11 - Srinivas Neeli <srinivas.neeli@amd.com>14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.15 WDT uses a dual-expiration architecture. After one expiration of16 the timeout interval, an interrupt is generated and the WDT state19 expiration of the timeout interval, a WDT reset is generated.[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2013 - 2014 Xilinx, Inc.21 /* Register offsets for the Wdt device */24 #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */29 #define XWT_CSR0_EWDT1_MASK BIT(1) /* Enable bit 1 */31 /* Control/Status Register 0/1 bits */54 ret = clk_enable(xdev->clk); in xilinx_wdt_start()56 dev_err(wdd->parent, "Failed to enable clock\n"); in xilinx_wdt_start()60 spin_lock(&xdev->spinlock); in xilinx_wdt_start()63 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()[all …]
5 ---------------------------------------------------21 W: *Web-page* with status/info23 B: URI for where to file *bugs*. A web-page with detailed bug28 patches to the given subsystem. This is either an in-tree file,29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst46 N: [^a-z]tegra all files whose path contains tegra64 ----------------83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)85 L: linux-scsi@vger.kernel.org88 F: drivers/scsi/3w-*[all …]