Searched +full:xmem +full:- +full:read +full:- +full:delta +full:- +full:cycles (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any11 external memory (such as NAND or other memory-mapped peripherals) whereas25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)[all …]
1 // SPDX-License-Identifier: GPL-2.0-only41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the42 * memory continues to drive the data bus after OE is de-asserted.43 * Inserted when reading one CS and switching to another CS or read45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first52 * read to a page or burst memory53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle54 * so 1 thru 16 cycles.[all …]
1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2 #include <dt-bindings/input/input.h>3 #include <dt-bindings/gpio/gpio.h>4 #include <dt-bindings/leds/common.h>5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>7 #include "qcom-msm8660.dtsi"12 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";19 stdout-path = "serial0:115200n8";23 vph: regulator-fixed {[all …]