Lines Matching +full:xmem +full:- +full:read +full:- +full:delta +full:- +full:cycles
1 // SPDX-License-Identifier: GPL-2.0-only
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
43 * Inserted when reading one CS and switching to another CS or read
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
52 * read to a page or burst memory
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
54 * so 1 thru 16 cycles.
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
56 * so 1 thru 16 cycles.
74 * Bits 31-28: ?
75 * Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
76 * transfer. For a single read trandfer this will be the time
78 * Bits 18-24: ?
79 * Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE
81 * 2 means 2 cycles between ADV and OE. Values 0, 1, 2 or 3.
85 * The manual mentions "write precharge cycles" and "precharge cycles".
103 * struct cs_data - struct with info on a chipselect setting
154 * struct ebi2_xmem_prop - describes an XMEM config property
171 .prop = "qcom,xmem-recovery-cycles",
177 .prop = "qcom,xmem-write-hold-cycles",
183 .prop = "qcom,xmem-write-delta-cycles",
189 .prop = "qcom,xmem-read-delta-cycles",
195 .prop = "qcom,xmem-write-wait-cycles",
201 .prop = "qcom,xmem-read-wait-cycles",
207 .prop = "qcom,xmem-address-hold-enable",
213 .prop = "qcom,xmem-adv-to-oe-recovery-cycles",
219 .prop = "qcom,xmem-read-hold-cycles",
240 val |= csd->enable_mask; in qcom_ebi2_setup_chipselect()
252 ret = of_property_read_u32(np, xp->prop, &val); in qcom_ebi2_setup_chipselect()
254 dev_dbg(dev, "could not read %s for CS%d\n", in qcom_ebi2_setup_chipselect()
255 xp->prop, csindex); in qcom_ebi2_setup_chipselect()
260 if (xp->max == 1 && val) { in qcom_ebi2_setup_chipselect()
261 if (xp->slowreg) in qcom_ebi2_setup_chipselect()
262 slowcfg |= BIT(xp->shift); in qcom_ebi2_setup_chipselect()
264 fastcfg |= BIT(xp->shift); in qcom_ebi2_setup_chipselect()
265 dev_dbg(dev, "set %s flag\n", xp->prop); in qcom_ebi2_setup_chipselect()
270 if (val > xp->max) { in qcom_ebi2_setup_chipselect()
273 xp->prop, val, xp->max); in qcom_ebi2_setup_chipselect()
274 val = xp->max; in qcom_ebi2_setup_chipselect()
276 if (xp->slowreg) in qcom_ebi2_setup_chipselect()
277 slowcfg |= (val << xp->shift); in qcom_ebi2_setup_chipselect()
279 fastcfg |= (val << xp->shift); in qcom_ebi2_setup_chipselect()
280 dev_dbg(dev, "set %s to %u\n", xp->prop, val); in qcom_ebi2_setup_chipselect()
287 writel(slowcfg, ebi2_xmem + csd->slow_cfg); in qcom_ebi2_setup_chipselect()
289 writel(fastcfg, ebi2_xmem + csd->fast_cfg); in qcom_ebi2_setup_chipselect()
294 struct device_node *np = pdev->dev.of_node; in qcom_ebi2_probe()
296 struct device *dev = &pdev->dev; in qcom_ebi2_probe()
363 "invalid chipselect %u, we only support 0-5\n", in qcom_ebi2_probe()
391 { .compatible = "qcom,msm8660-ebi2", },
392 { .compatible = "qcom,apq8060-ebi2", },
399 .name = "qcom-ebi2",