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/linux/drivers/thunderbolt/
H A Dxdomain.c155 * @xd: XDomain to send the message
165 int tb_xdomain_response(struct tb_xdomain *xd, const void *response, in tb_xdomain_response() argument
168 return __tb_xdomain_response(xd->tb->ctl, response, size, type); in tb_xdomain_response()
202 * @xd: XDomain to send the request
217 int tb_xdomain_request(struct tb_xdomain *xd, const void *request, in tb_xdomain_request() argument
222 return __tb_xdomain_request(xd->tb->ctl, request, request_size, in tb_xdomain_request()
415 struct tb_xdomain *xd, u8 sequence, const struct tb_xdp_properties *req) in tb_xdp_properties_response() argument
427 if (!uuid_equal(xd->local_uuid, &req->dst_uuid)) { in tb_xdp_properties_response()
428 tb_xdp_error_response(ctl, xd->route, sequence, in tb_xdp_properties_response()
433 mutex_lock(&xd->lock); in tb_xdp_properties_response()
[all …]
H A Dicm.c383 static void icm_xdomain_activated(struct tb_xdomain *xd, bool activated) in icm_xdomain_activated() argument
386 struct tb *tb = xd->tb; in icm_xdomain_activated()
389 dst_port = tb_xdomain_downstream_port(xd); in icm_xdomain_activated()
582 static int icm_fr_approve_xdomain_paths(struct tb *tb, struct tb_xdomain *xd, in icm_fr_approve_xdomain_paths() argument
592 request.link_info = xd->depth << ICM_LINK_INFO_DEPTH_SHIFT | xd->link; in icm_fr_approve_xdomain_paths()
593 memcpy(&request.remote_uuid, xd->remote_uuid, sizeof(*xd->remote_uuid)); in icm_fr_approve_xdomain_paths()
609 icm_xdomain_activated(xd, true); in icm_fr_approve_xdomain_paths()
613 static int icm_fr_disconnect_xdomain_paths(struct tb *tb, struct tb_xdomain *xd, in icm_fr_disconnect_xdomain_paths() argument
620 phy_port = tb_phy_port_from_link(xd->link); in icm_fr_disconnect_xdomain_paths()
630 icm_xdomain_activated(xd, false); in icm_fr_disconnect_xdomain_paths()
[all …]
H A Ddma_test.c72 * @xd: XDomain the service belongs to
94 struct tb_xdomain *xd; member
125 tb_xdomain_release_in_hopid(dt->xd, dt->rx_hopid); in dma_test_free_rings()
130 tb_xdomain_release_out_hopid(dt->xd, dt->tx_hopid); in dma_test_free_rings()
139 struct tb_xdomain *xd = dt->xd; in dma_test_start_rings() local
152 ring = tb_ring_alloc_tx(xd->tb->nhi, -1, DMA_TEST_TX_RING_SIZE, in dma_test_start_rings()
160 ret = tb_xdomain_alloc_out_hopid(xd, -1); in dma_test_start_rings()
175 ring = tb_ring_alloc_rx(xd->tb->nhi, -1, DMA_TEST_RX_RING_SIZE, in dma_test_start_rings()
185 ret = tb_xdomain_alloc_in_hopid(xd, -1); in dma_test_start_rings()
194 ret = tb_xdomain_enable_paths(dt->xd, dt->tx_hopid, in dma_test_start_rings()
[all …]
/linux/fs/jffs2/
H A Dxattr.c32 * is_xattr_datum_unchecked(c, xd)
35 * unload_xattr_datum(c, xd)
41 * do_verify_xattr_datum(c, xd)
48 * do_load_xattr_datum(c, xd)
51 * load_xattr_datum(c, xd)
53 * If xd need to call do_verify_xattr_datum() at first, it's called before calling
55 * save_xattr_datum(c, xd)
56 * is used to write xdatum to medium. xd->version will be incremented.
59 * unrefer_xattr_datum(c, xd)
61 * is set on xd->flags and chained xattr_dead_list or release it immediately.
[all …]
/linux/arch/powerpc/sysdev/xive/
H A Dcommon.c92 static bool xive_is_store_eoi(struct xive_irq_data *xd) in xive_is_store_eoi() argument
94 return xd->flags & XIVE_IRQ_FLAG_STORE_EOI && xive_store_eoi; in xive_is_store_eoi()
217 static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset) in xive_esb_read() argument
221 if (offset == XIVE_ESB_SET_PQ_10 && xive_is_store_eoi(xd)) in xive_esb_read()
224 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw) in xive_esb_read()
225 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0); in xive_esb_read()
227 val = in_be64(xd->eoi_mmio + offset); in xive_esb_read()
232 static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data) in xive_esb_write() argument
234 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw) in xive_esb_write()
235 xive_ops->esb_rw(xd->hw_irq, offset, data, 1); in xive_esb_write()
[all …]
/linux/drivers/net/thunderbolt/
H A Dmain.c152 * @xd: XDomain the service belongs to
183 struct tb_xdomain *xd;
245 struct tb_xdomain *xd = net->xd; in tbnet_login_response()
248 tbnet_fill_header(&reply.hdr, route, sequence, xd->local_uuid, in tbnet_login_response()
249 xd->remote_uuid, TBIP_LOGIN_RESPONSE, sizeof(reply), in tbnet_login_response()
254 return tb_xdomain_response(xd, &reply, sizeof(reply), in tbnet_login_response()
262 struct tb_xdomain *xd = net->xd; in tbnet_login_request()
265 tbnet_fill_header(&request.hdr, xd in tbnet_login_request()
182 struct tb_xdomain *xd; global() member
244 struct tb_xdomain *xd = net->xd; tbnet_login_response() local
261 struct tb_xdomain *xd = net->xd; tbnet_login_request() local
281 struct tb_xdomain *xd = net->xd; tbnet_logout_response() local
295 struct tb_xdomain *xd = net->xd; tbnet_logout_request() local
919 struct tb_xdomain *xd = net->xd; tbnet_open() local
1270 const struct tb_xdomain *xd = net->xd; tbnet_generate_mac() local
1288 struct tb_xdomain *xd = tb_service_parent(svc); tbnet_probe() local
[all...]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_0_1_sh_mask.h34 …RDCLI0__MAX_BW__SHIFT 0xd
55 …RDCLI1__MAX_BW__SHIFT 0xd
76 …RDCLI2__MAX_BW__SHIFT 0xd
97 …RDCLI3__MAX_BW__SHIFT 0xd
118 …RDCLI4__MAX_BW__SHIFT 0xd
139 …RDCLI5__MAX_BW__SHIFT 0xd
160 …RDCLI6__MAX_BW__SHIFT 0xd
181 …RDCLI7__MAX_BW__SHIFT 0xd
202 …RDCLI8__MAX_BW__SHIFT 0xd
223 …RDCLI9__MAX_BW__SHIFT 0xd
[all …]
H A Dmmhub_3_0_2_sh_mask.h34 …RDCLI0__MAX_BW__SHIFT 0xd
55 …RDCLI1__MAX_BW__SHIFT 0xd
76 …RDCLI2__MAX_BW__SHIFT 0xd
97 …RDCLI3__MAX_BW__SHIFT 0xd
118 …RDCLI4__MAX_BW__SHIFT 0xd
139 …RDCLI5__MAX_BW__SHIFT 0xd
160 …RDCLI6__MAX_BW__SHIFT 0xd
181 …RDCLI7__MAX_BW__SHIFT 0xd
202 …RDCLI8__MAX_BW__SHIFT 0xd
223 …RDCLI9__MAX_BW__SHIFT 0xd
[all …]
H A Dmmhub_3_0_0_sh_mask.h34 …RDCLI0__MAX_BW__SHIFT 0xd
55 …RDCLI1__MAX_BW__SHIFT 0xd
76 …RDCLI2__MAX_BW__SHIFT 0xd
97 …RDCLI3__MAX_BW__SHIFT 0xd
118 …RDCLI4__MAX_BW__SHIFT 0xd
139 …RDCLI5__MAX_BW__SHIFT 0xd
160 …RDCLI6__MAX_BW__SHIFT 0xd
181 …RDCLI7__MAX_BW__SHIFT 0xd
202 …RDCLI8__MAX_BW__SHIFT 0xd
223 …RDCLI9__MAX_BW__SHIFT 0xd
[all …]
H A Dmmhub_4_1_0_sh_mask.h34 …RDCLI0__MAX_BW__SHIFT 0xd
55 …RDCLI1__MAX_BW__SHIFT 0xd
76 …RDCLI2__MAX_BW__SHIFT 0xd
97 …RDCLI3__MAX_BW__SHIFT 0xd
118 …RDCLI4__MAX_BW__SHIFT 0xd
139 …RDCLI5__MAX_BW__SHIFT 0xd
160 …RDCLI6__MAX_BW__SHIFT 0xd
181 …RDCLI7__MAX_BW__SHIFT 0xd
202 …RDCLI8__MAX_BW__SHIFT 0xd
223 …RDCLI9__MAX_BW__SHIFT 0xd
[all …]
H A Dmmhub_3_3_0_sh_mask.h34 …RDCLI0__MAX_BW__SHIFT 0xd
55 …RDCLI1__MAX_BW__SHIFT 0xd
76 …RDCLI2__MAX_BW__SHIFT 0xd
97 …RDCLI3__MAX_BW__SHIFT 0xd
118 …RDCLI4__MAX_BW__SHIFT 0xd
139 …RDCLI5__MAX_BW__SHIFT 0xd
160 …RDCLI6__MAX_BW__SHIFT 0xd
181 …RDCLI7__MAX_BW__SHIFT 0xd
202 …RDCLI8__MAX_BW__SHIFT 0xd
223 …RDCLI9__MAX_BW__SHIFT 0xd
[all …]
H A Dmmhub_2_3_0_sh_mask.h32 …RDCLI0__MAX_BW__SHIFT 0xd
53 …RDCLI1__MAX_BW__SHIFT 0xd
74 …RDCLI2__MAX_BW__SHIFT 0xd
95 …RDCLI3__MAX_BW__SHIFT 0xd
116 …RDCLI4__MAX_BW__SHIFT 0xd
137 …RDCLI5__MAX_BW__SHIFT 0xd
158 …RDCLI6__MAX_BW__SHIFT 0xd
179 …RDCLI7__MAX_BW__SHIFT 0xd
200 …RDCLI8__MAX_BW__SHIFT 0xd
221 …RDCLI9__MAX_BW__SHIFT 0xd
[all …]
H A Dmmhub_1_8_0_sh_mask.h34 …RDCLI0__MAX_BW__SHIFT 0xd
55 …RDCLI1__MAX_BW__SHIFT 0xd
76 …RDCLI2__MAX_BW__SHIFT 0xd
97 …RDCLI3__MAX_BW__SHIFT 0xd
118 …RDCLI4__MAX_BW__SHIFT 0xd
139 …RDCLI5__MAX_BW__SHIFT 0xd
160 …RDCLI6__MAX_BW__SHIFT 0xd
181 …RDCLI7__MAX_BW__SHIFT 0xd
202 …RDCLI8__MAX_BW__SHIFT 0xd
223 …RDCLI9__MAX_BW__SHIFT 0xd
[all …]
/linux/drivers/mtd/nand/raw/
H A Dsm_common.c4 * Common routines & support for xD format
150 LEGACY_ID_NAND("xD 16MiB 3,3V", 0x73, 16, SZ_16K, 0),
151 LEGACY_ID_NAND("xD 32MiB 3,3V", 0x75, 32, SZ_16K, 0),
152 LEGACY_ID_NAND("xD 64MiB 3,3V", 0x76, 64, SZ_16K, 0),
153 LEGACY_ID_NAND("xD 128MiB 3,3V", 0x79, 128, SZ_16K, 0),
154 LEGACY_ID_NAND("xD 256MiB 3,3V", 0x71, 256, SZ_16K, NAND_BROKEN_XD),
155 LEGACY_ID_NAND("xD 512MiB 3,3V", 0xdc, 512, SZ_16K, NAND_BROKEN_XD),
156 LEGACY_ID_NAND("xD 1GiB 3,3V", 0xd3, 1024, SZ_16K, NAND_BROKEN_XD),
157 LEGACY_ID_NAND("xD 2GiB 3,3V", 0xd5, 2048, SZ_16K, NAND_BROKEN_XD),
210 MODULE_DESCRIPTION("Common SmartMedia/xD functions");
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_3_sh_mask.h430 …X0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
479 …X0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
664 …X0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd
923 …X0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd
1069 …X1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
1118 …X1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
1303 …X1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd
1562 …X1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd
1708 …X2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
1757 …X2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
[all …]
H A Ddpcs_3_1_4_sh_mask.h44 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT 0xd
103 …S_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT 0xd
189 …S_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT 0xd
575 …S_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd
667 …S_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT 0xd
843 …S_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT 0xd
888 …S_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT 0xd
1005 …S_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT 0xd
1029 …S_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT 0xd
1047 …S_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT 0xd
[all …]
H A Ddpcs_4_2_0_sh_mask.h422 …X0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
471 …X0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
641 …X0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd
900 …X0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd
1035 …X1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
1084 …X1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
1254 …X1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd
1513 …X1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd
1648 …X2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
1697 …X2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
[all …]
H A Ddpcs_4_2_2_sh_mask.h413 …X0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
462 …X0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
647 …X0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd
906 …X0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd
1052 …X1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
1101 …X1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
1286 …X1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT 0xd
1545 …X1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT 0xd
1691 …X2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT 0xd
1740 …X2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT 0xd
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp-pinfunc.h20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
29 #define MX8ULP_PAD_PTD1__LP_APD_DBG_MUX_1 0x0004 0x0000 0xd 0x0
38 #define MX8ULP_PAD_PTD2__LP_APD_DBG_MUX_2 0x0008 0x0000 0xd 0x0
47 #define MX8ULP_PAD_PTD3__LP_APD_DBG_MUX_3 0x000C 0x0000 0xd 0x0
59 #define MX8ULP_PAD_PTD4__LP_APD_DBG_MUX_4 0x0010 0x0000 0xd 0x0
71 #define MX8ULP_PAD_PTD5__LP_APD_DBG_MUX_5 0x0014 0x0000 0xd 0x0
82 #define MX8ULP_PAD_PTD6__LP_APD_DBG_MUX_6 0x0018 0x0000 0xd 0x0
92 #define MX8ULP_PAD_PTD7__LP_APD_DBG_MUX_7 0x001C 0x0000 0xd 0x0
151 #define MX8ULP_PAD_PTD13__CLKOUT1 0x0034 0x0000 0xd 0x0
248 #define MX8ULP_PAD_PTD21__WDOG5_RST 0x0054 0x0000 0xd 0x0
[all …]
/linux/sound/pci/au88x0/
H A Dau88x0_wt.h21 #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */
22 #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */
23 #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */
24 #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */
25 #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */
26 #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */
/linux/drivers/gpio/
H A Dgpio-104-dio-48e.c42 #define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD
50 regmap_reg_range(0xD, 0xD), regmap_reg_range(0xF, 0xF),
54 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
59 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
63 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
101 {170000000, 0x71, 0x55, 0x3, 0xb, 0x18, 0x11, 0x5, 0x2e, 0xd, 0x7, 0x3d},
105 {320000000, 0x6a, 0xaa, 0x2, 0x8, 0x14, 0xf, 0x5, 0x2b, 0xd, 0x3, 0x23},
106 {330000000, 0x6e, 0x0, 0x2, 0x8, 0x15, 0xf, 0x5, 0x2d, 0xd, 0x3, 0x23},
107 {340000000, 0x71, 0x55, 0x2, 0x9, 0x15, 0xf, 0x5, 0x2e, 0xd, 0x3, 0x23},
125 {520000000, 0xad, 0x55, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x45, 0x13, 0x3, 0x29},
126 {530000000, 0xb0, 0xaa, 0x2, 0xd, 0x1e, 0x15, 0x9, 0x47, 0x13, 0x3, 0x29},
127 {540000000, 0xb4, 0x0, 0x2, 0xd, 0x1f, 0x15, 0x9, 0x48, 0x13, 0x3, 0x29},
128 {550000000, 0xb7, 0x55, 0x2, 0xd, 0x20, 0x16, 0x9, 0x4a, 0x14, 0x3, 0x2a},
136 {630000000, 0x69, 0x0, 0x1, 0x7, 0x12, 0xd, 0x5, 0x2a, 0xc, 0x1, 0x15},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h62 #define BUS_CNTL__SET_MC_TC__SHIFT 0xd
158 #define HW_DEBUG__HW_13_DEBUG__SHIFT 0xd
226 #define INTERRUPT_CNTL__SELECT_INT_GPIO_OUTPUT__SHIFT 0xd
290 #define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd
328 #define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd
418 #define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd
576 #define BACO_CNTL__PWRGOOD_IDSC__SHIFT 0xd
740 #define GARLIC_FLUSH_CNTL__HOST_DOORBELL__SHIFT 0xd
848 #define GPU_GARLIC_FLUSH_REQ__SDMA3__SHIFT 0xd
876 #define GPU_GARLIC_FLUSH_DONE__SDMA3__SHIFT 0xd
[all …]
/linux/arch/powerpc/kvm/
H A Dbook3s_xive.c33 #define __x_eoi_page(xd) ((void __iomem *)((xd)->eoi_mmio)) argument
34 #define __x_trig_page(xd) ((void __iomem *)((xd)->trig_mmio)) argument
80 static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset) in xive_vm_esb_load() argument
84 if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI) in xive_vm_esb_load()
87 val = __raw_readq(__x_eoi_page(xd) + offset); in xive_vm_esb_load()
95 static void xive_vm_source_eoi(u32 hw_irq, struct xive_irq_data *xd) in xive_vm_source_eoi() argument
98 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) in xive_vm_source_eoi()
99 __raw_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI); in xive_vm_source_eoi()
100 else if (xd->flags & XIVE_IRQ_FLAG_LSI) { in xive_vm_source_eoi()
106 __raw_readq(__x_eoi_page(xd) + XIVE_ESB_LOAD_EOI); in xive_vm_source_eoi()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_enum.h67 IH_PERF_SEL_RB_OVERFLOW = 0xd,
106 SRBM_PERF_SEL_XSP_BUSY = 0xd,
135 GRBM_GFX_INDEX_SDMA2 = 0xd,
152 SRBM_GFX_CNTL_SDMA2 = 0xd,
169 SDMA_PERF_SEL_EX_IDLE = 0xd,
232 ARRAY_3D_TILED_THICK = 0xd,
330 DBG_CLIENT_BLKID_uvdf_1 = 0xd,
470 DBG_BLOCK_ID_AVP = 0xd,
704 DBG_BLOCK_ID_CP2_BY2 = 0xd,
822 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
[all …]

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