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/linux/Documentation/devicetree/bindings/net/
H A Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAC in Ingenic SoCs
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
[all …]
H A Dqcom-emac.txt3 This network controller consists of two devices: a MAC and an SGMII
5 connects the MAC node to its corresponding internal phy node. Another
10 MAC node:
11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
15 MAC address.
16 - internal-phy : phandle to the internal PHY node
17 - phy-handle : phandle to the external PHY node
[all …]
H A Dhisilicon-femac.txt1 Hisilicon Fast Ethernet MAC controller
4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
9 The first region is the MAC core register base and size.
10 The second region is the global MAC control register.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
[all …]
H A Dfsl,gianfar.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Three-Speed Ethernet Controller (TSEC), "Gianfar"
10 - J. Neuschäfer <j.ne@posteo.net>
12 # This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because
16 - properties:
23 - device_type
25 - properties:
30 - compatible
[all …]
/linux/arch/powerpc/boot/dts/
H A Dksi8560.dts15 /dts-v1/;
22 #address-cells = <1>;
23 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
38 d-cache-line-size = <32>;
39 i-cache-line-size = <32>;
40 d-cache-size = <0x8000>; /* L1, 32K */
41 i-cache-size = <0x8000>; /* L1, 32K */
42 timebase-frequency = <0>; /* From U-boot */
[all …]
H A Dxpedite5200.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dtqm8540.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>;
35 i-cache-line-size = <32>;
36 d-cache-size = <32768>;
37 i-cache-size = <32768>;
[all …]
H A Dtqm8548.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dtqm8548-bigflash.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5200_xmon.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 * xMon boot loader memory map which differs from U-Boot's.
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <32>; // 32 bytes
[all …]
H A Dtqm8560.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal1.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
36 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
37 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
38 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
49 #define MV88E6352_G1_VTU_FID_VID_POLICY 0x1000
78 #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
93 #define MV88E6XXX_G1_VTU_VID_VALID 0x1000
122 #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000
166 /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
[all …]
H A Dglobal2.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
21 #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
33 #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000
41 /* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */
47 /* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */
86 #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000
104 /* Offset 0x0B: Cross-chip Port VLAN Register */
108 #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000
114 /* Offset 0x0C: Cross-chip Port VLAN Data Register */
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Dx1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
4 #include <dt-bindings/dma/x1000-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "ingenic,x1000", "ingenic,x1000e";
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
[all …]
H A Dx1830.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,tcu.h>
3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
4 #include <dt-bindings/dma/x1830-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu2.0-mxu2.0";
21 clock-names = "cpu";
[all …]
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x4000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
H A Dkeystone-k2e-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
H A Dkeystone-k2l-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
15 queue-range = <0 0x2000>;
20 #address-cells = <1>;
21 #size-cells = <1>;
24 managed-queues = <0 0x2000>;
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
27 - mediatek,mt8186-mtu3
[all …]
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/linux/arch/mips/ath25/
H A Dboard.c9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
49 if (check_radio_magic(addr + 0x1000)) in check_board_data()
61 const void __iomem *begin = limit - 0x1000; in find_board_config()
62 const void __iomem *end = limit - 0x30000; in find_board_config()
64 for (addr = begin; addr >= end; addr -= 0x1000) in find_board_config()
78 * Search forward from Board Configuration data by 0x1000 bytes in find_radio_config()
79 * at a time until we find non-0xffffffff. in find_radio_config()
81 begin = bcfg + 0x1000; in find_radio_config()
83 for (rcfg = begin; rcfg < end; rcfg += 0x1000) in find_radio_config()
89 end = limit - 0x1000 + 0xf8; in find_radio_config()
[all …]
/linux/drivers/net/ethernet/agere/
H A Det131x.h52 /* LBCIF Register Groups (addressed via 32-bit offsets) */
56 /* LBCIF Registers (addressed via 8-bit offsets) */
174 /* txdma control status reg at address 0x1000
196 * 31-10: unused
197 * 9-0: pr ndes
200 #define ET_DMA12_WRAP 0x1000
237 * Located at address 0x1000
240 u32 csr; /* 0x1000 */
276 * 1-3: tc
281 * 8-9: fbr0_size
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
99 #define TWSI_CTRL_HW_LDSTART 0x1000
120 #define REG_PCIE_PHYMISC 0x1000
149 /* IRQ Anti-Lost Timer Initial Value Register */
192 /* MAC Control Register */
[all …]

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