| /linux/include/soc/at91/ |
| H A D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
114 #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
[all …]
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| /linux/arch/mips/sgi-ip22/ |
| H A D | ip22-nvram.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ip22-nvram.c: NVRAM and serial EEPROM handling.
5 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
14 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
15 #define EEPROM_WRITE 0xa000 /* serial memory write */
16 #define EEPROM_WRALL 0x8800 /* write all registers */
18 #define EEPROM_PRREAD 0xc000 /* read protect register */
19 #define EEPROM_PREN 0x9800 /* enable protect register mode */
20 #define EEPROM_PRCLEAR 0xffff /* clear protect register */
21 #define EEPROM_PRWRITE 0xa000 /* write protect register */
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| /linux/security/ |
| H A D | min_addr.c | 1 // SPDX-License-Identifier: GPL-2.0
8 /* amount of vm to protect from userspace access by both DAC and the LSM*/
10 /* amount of vm to protect from userspace using CAP_SYS_RAWIO (DAC) */
12 /* amount of vm to protect from userspace using the LSM = CONFIG_LSM_MMAP_MIN_ADDR */
30 int mmap_min_addr_handler(const struct ctl_table *table, int write, in mmap_min_addr_handler() argument
35 if (write && !capable(CAP_SYS_RAWIO)) in mmap_min_addr_handler()
36 return -EPERM; in mmap_min_addr_handler()
38 ret = proc_doulongvec_minmax(table, write, buffer, lenp, ppos); in mmap_min_addr_handler()
|
| /linux/drivers/gpib/ni_usb/ |
| H A D | ni_usb_gpib.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
75 struct mutex addressed_transfer_lock; // protect transfer lock
76 struct mutex bulk_transfer_lock; // protect bulk message sends
77 struct mutex control_transfer_lock; // protect control messages
78 struct mutex interrupt_transfer_lock; // protect interrupt messages
128 * read/write as CIC but are not in LACS/TACS
135 * command bytes at once on a usb-b.
139 * NIUSB_NO_BUS_ERROR occurs when you try to write a command
144 * NIUSB_NO_LISTENER_ERROR occurs when you do a board write as
148 /* get NIUSB_TIMEOUT_ERROR on board read/write timeout */
|
| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | mmc-controller-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
34 cd-gpios:
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| /linux/drivers/rtc/ |
| H A D | rtc-max6900.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 #define MAX6900_REG_SC 0 /* seconds 00-59 */
22 #define MAX6900_REG_MN 1 /* minutes 00-59 */
23 #define MAX6900_REG_HR 2 /* hours 00-23 */
24 #define MAX6900_REG_DT 3 /* day of month 00-31 */
25 #define MAX6900_REG_MO 4 /* month 01-12 */
26 #define MAX6900_REG_DW 5 /* day of week 1-7 */
27 #define MAX6900_REG_YR 6 /* year 00-99 */
35 #define MAX6900_REG_CT_WP (1 << 7) /* Write Protect */
38 * register read/write commands
[all …]
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| /linux/fs/jffs2/ |
| H A D | jffs2_fs_sb.h | 2 * JFFS2 -- Journalling Flash File System, Version 2.
4 * Copyright © 2001-2007 Red Hat, Inc.
5 * Copyright © 2004-2010 David Woodhouse <dwmw2@infradead.org>
39 * latter users to write to the file system if the amount if the
61 struct mutex alloc_sem; /* Used to protect all the following
62 fields, and also to protect against
63 out-of-order writing of nodes. And GC. */
81 uint8_t resv_blocks_write; /* ... allow a normal filesystem write */
96 struct jffs2_eraseblock *gcblock; /* The block we're currently garbage-collecting */
111 spinlock_t erase_completion_lock; /* Protect free_list and erasing_list
[all …]
|
| H A D | README.Locking | 3 ---------------------------
11 ---------
13 The alloc_sem is a per-filesystem mutex, used primarily to ensure
16 upon write completion (jffs2_complete_reservation()). Note that
19 preventing any other write activity on the file system during a
24 which they belong. This is for the benefit of NAND flash - adding new
26 until this happens we ensure that any data in the write-buffer at the
28 was written afterwards. Hence, we can ensure the newly-obsoleted nodes
29 don't actually get erased until the write-buffer has been flushed to
32 With the introduction of NAND flash support and the write-buffer,
[all …]
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| /linux/drivers/iio/dac/ |
| H A D | ad5446.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
38 * struct ad5446_state - driver instance specific data
45 * @lock: lock to protect the data buffer during write ops
54 /* mutex to protect device shared data */
63 * struct ad5446_chip_info - chip specific information
66 * @write: chip specific helper function to write to the register
71 int (*write)(struct ad5446_state *st, unsigned int val); member
|
| /linux/include/linux/ |
| H A D | fsl_ifc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
35 * CSPR - Chip Select Property Register
47 /* Write Protect */
69 (__ilog2(n) - IFC_AMASK_SHIFT))
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
123 * Chip Select Option Register - NOR Flash Mode
150 * Chip Select Option Register - GPCM Mode
152 /* GPCM Mode - Normal */
[all …]
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| /linux/include/linux/clk/ |
| H A D | at91_pmc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
55 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
57 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
69 #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
70 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
186 #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
207 #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
219 #define AT91_PMC_LPM BIT(20) /* Low-power Mode */
229 #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
[all …]
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| /linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | nvmem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
23 "#address-cells":
26 "#size-cells":
29 read-only:
34 wp-gpios:
36 GPIO to which the write-protect pin of the chip is connected.
37 The write-protect GPIO is asserted, when it's driven high
[all …]
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| /linux/tools/laptop/freefall/ |
| H A D | freefall.c | 1 // SPDX-License-Identifier: GPL-2.0-only
32 return -EINVAL; in set_unload_heads_path()
33 strncpy(device_path, device, sizeof(device_path) - 1); in set_unload_heads_path()
35 snprintf(unload_heads_path, sizeof(unload_heads_path) - 1, in set_unload_heads_path()
65 if (write(fd, buf, strlen(buf)) != strlen(buf)) { in write_int()
66 perror("write"); in write_int()
80 static void protect(int seconds) in protect() function
102 protect(0); in ignore_me()
117 ret = -EINVAL; in main()
152 if ((ret == -1) && (errno == EINTR)) { in main()
[all …]
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| /linux/arch/m68k/include/asm/ |
| H A D | m53xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m53xxacr.h -- ColdFire version 3 core cache support
18 * configurable write-through or copy-back operation.
30 #define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
31 #define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
34 #define CACR_WPROTECT 0x00000020 /* Write protect*/
46 #define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
47 #define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
50 #define ACR_WPROTECT 0x00000004 /* Write protect region */
66 #define CACHE_WAYS 4 /* 4 ways - set associative */
[all …]
|
| H A D | m54xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define CACR_DWP 0x40000000 /* Data write protection */
17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
44 #define ACR_WPROTECT 0x00000004 /* Write protect */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
51 #define ICACHE_SIZE 0x4000 /* instruction - 16k */
52 #define DCACHE_SIZE 0x2000 /* data - 8k */
56 #define ICACHE_SIZE 0x8000 /* instruction - 32k */
[all …]
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | arm,pl172.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
22 - compatible
27 - enum:
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| /linux/include/xen/interface/ |
| H A D | features.h | 1 /* SPDX-License-Identifier: MIT */
14 * If set, the guest does not need to write-protect its pagetables, and can
20 * If set, the guest does not need to write-protect its segment descriptor
26 * If set, translation between the guest's 'pseudo-physical' address space
28 * mode the guest does not need to perform phys-to/from-machine translations
79 * must be located in lower 1MB, as required by ACPI Specification for IA-PC
87 * A direct-mapped (or 1:1 mapped) domain is a domain for which its
88 * local pages have gfn == mfn. If a domain is direct-mapped,
93 * - not auto_translated domains (x86 only) are always direct-mapped
94 * - on x86, auto_translated domains are not direct-mapped
[all …]
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| /linux/Documentation/userspace-api/gpio/ |
| H A D | sysfs.rst | 6 been moved to Documentation/ABI/obsolete/sysfs-gpio.
16 ----------------------
24 know for example that GPIO #23 controls the write protect line used to
25 protect boot loader segments in flash memory. System upgrade procedures
27 then changing its output state, then updating the code before re-enabling
28 the write protection. In normal use, GPIO #23 would never be touched,
38 Please read Documentation/driver-api/gpio/drivers-on-gpio.rst
44 --------------
47 - Control interfaces used to get userspace control over GPIOs;
49 - GPIOs themselves; and
[all …]
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| /linux/Documentation/locking/ |
| H A D | spinlocks.rst | 20 there is only one thread-of-control within the region(s) protected by that
26 Documentation/memory-barriers.txt
33 spinlock for most things - using more than one spinlock can make things a
40 before, because you have to make sure the spinlocks correctly protect the
45 NOTE! The spin-lock is safe only when you **also** use the lock itself
50 ----
52 Lesson 2: reader-writer spinlocks.
56 to mostly read from the shared variables, the reader-writer locks
59 to change the variables it has to get an exclusive write lock.
61 NOTE! reader-writer locks require more atomic memory operations than
[all …]
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| /linux/drivers/misc/ |
| H A D | sram-exec.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * SRAM protect-exec region helper functions
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
25 unsigned long base = (unsigned long)part->base; in sram_check_protect_exec()
26 unsigned long end = base + block->size; in sram_check_protect_exec()
29 dev_err(sram->dev, in sram_check_protect_exec()
30 "SRAM pool marked with 'protect-exec' is not page aligned and will not be created.\n"); in sram_check_protect_exec()
31 return -ENOMEM; in sram_check_protect_exec()
40 list_add_tail(&part->list, &exec_pool_list); in sram_add_protect_exec()
47 * sram_exec_copy - copy data to a protected executable region of sram
[all …]
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| /linux/include/uapi/linux/ |
| H A D | fdreg.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
30 /* Diskette Control Register (write)*/
36 #define STATUS_DMA 0x20 /* 0- DMA mode */
37 #define STATUS_DIR 0x40 /* 0- cpu->fdc */
50 #define ST1_WP 0x02 /* Write Protect */
51 #define ST1_ND 0x04 /* No Data - unreadable */
67 #define ST3_DS 0x08 /* drive is double-sided */
70 #define ST3_WP 0x40 /* Write Protect */
77 #define FD_WRITE 0xC5 /* write with MT, MFM */
105 #define FD_FORMAT_N_WRITE 0xef /* format and write in one go. */
[all …]
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| /linux/drivers/media/platform/mediatek/vcodec/decoder/ |
| H A D | vdec_msg_queue.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <media/videobuf2-v4l2.h>
23 * enum core_ctx_status - Context decode status for core hardwre.
35 * struct vdec_msg_queue_ctx - represents a queue for buffers ready to be processed
38 * @ready_lock: spin lock to protect the lat buffer usage
45 /* protect lat buffer */
52 * struct vdec_lat_buf - lat buffer message used to store lat info for core decode
86 * struct vdec_msg_queue - used to store lat buffer message
90 * @wdma_wptr_addr: ube write point
124 * vdec_msg_queue_init - init lat buffer information.
[all …]
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| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | lpc32xx-slc.txt | 4 - compatible: "nxp,lpc3220-slc"
5 - reg: Address and size of the controller
6 - nand-on-flash-bbt: Use bad block table on flash
7 - gpios: GPIO specification for NAND write protect
11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
15 - nxp,wwidth: Write pulse width (W_WIDTH)
16 - nxp,whold: Write hold time (W_HOLD)
17 - nxp,wsetup: Write setup time (W_SETUP)
18 - nxp,rwidth: Read pulse width (R_WIDTH)
[all …]
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| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | param.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
15 #define OPTION_UNSET -1
37 * Tx interrupt delay needs to typically be set to something non-zero
39 * Valid Range: 0-65535
48 * Valid Range: 0-65535
60 * Valid Range: 0-65535
72 * Valid Range: 0-65535
82 * Valid Range: 100-100000 or one of: 0=off, 1=dynamic, 3=dynamic conservative
93 * legacy=0, MSI=1, MSI-X=2
[all …]
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| /linux/arch/mips/sibyte/swarm/ |
| H A D | rtc_xicor1241.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
28 #define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
31 #define X1241REG_BL_BP2 0x80 /* block protect 2 */
32 #define X1241REG_BL_BP1 0x40 /* block protect 1 */
33 #define X1241REG_BL_BP0 0x20 /* block protect 0 */
42 #define X1241REG_BL 0x10 /* block protect bits */
80 return -1; in xicor_read()
102 return -1; in xicor_write()
154 tm.tm_hour -= 12; in xicor_set_time()
205 return xicor_read(X1241REG_SC) != -1; in xicor_probe()
|