| /linux/include/soc/at91/ |
| H A D | at91sam9_ddrsdr.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
114 #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
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| /linux/arch/mips/sgi-ip22/ |
| H A D | ip22-nvram.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * ip22-nvram.c: NVRAM and serial EEPROM handling.
5 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
14 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
15 #define EEPROM_WRITE 0xa000 /* serial memory write */
16 #define EEPROM_WRALL 0x8800 /* write all registers */
18 #define EEPROM_PRREAD 0xc000 /* read protect register */
19 #define EEPROM_PREN 0x9800 /* enable protect register mode */
20 #define EEPROM_PRCLEAR 0xffff /* clear protect register */
21 #define EEPROM_PRWRITE 0xa000 /* write protect register */
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| /linux/include/linux/mtd/ |
| H A D | spi-nor.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <linux/spi/spi-mem.h>
18 * requires a 4-byte (32-bit) address.
22 #define SPINOR_OP_WRDI 0x04 /* Write disable */
23 #define SPINOR_OP_WREN 0x06 /* Write enable */
25 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
27 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
53 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
71 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
85 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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| /linux/security/ |
| H A D | min_addr.c | 1 // SPDX-License-Identifier: GPL-2.0
8 /* amount of vm to protect from userspace access by both DAC and the LSM*/
10 /* amount of vm to protect from userspace using CAP_SYS_RAWIO (DAC) */
12 /* amount of vm to protect from userspace using the LSM = CONFIG_LSM_MMAP_MIN_ADDR */
30 int mmap_min_addr_handler(const struct ctl_table *table, int write, in mmap_min_addr_handler() argument
35 if (write && !capable(CAP_SYS_RAWIO)) in mmap_min_addr_handler()
36 return -EPERM; in mmap_min_addr_handler()
38 ret = proc_doulongvec_minmax(table, write, buffer, lenp, ppos); in mmap_min_addr_handler()
|
| /linux/drivers/usb/gadget/function/ |
| H A D | g_zero.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * interfaces to its two single-configuration function drivers.
41 * Read/write access to configfs attributes is handled by configfs.
43 * This is to protect the data from concurrent access by read/write
56 * Read/write access to configfs attributes is handled by configfs.
58 * This is to protect the data from concurrent access by read/write
|
| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | mmc-controller-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
34 cd-gpios:
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| /linux/Documentation/admin-guide/device-mapper/ |
| H A D | dm-integrity.rst | 2 dm-integrity
5 The dm-integrity target emulates a block device that has additional
6 per-sector tags that can be used for storing integrity information.
9 writing the sector and the integrity tag must be atomic - i.e. in case of
12 To guarantee write atomicity, the dm-integrity target uses journal, it
16 The dm-integrity target can be used with the dm-crypt target - in this
17 situation the dm-crypt target creates the integrity data and passes them
18 to the dm-integrity target via bio_integrity_payload attached to the bio.
19 In this mode, the dm-crypt and dm-integrity targets provide authenticated
20 disk encryption - if the attacker modifies the encrypted device, an I/O
[all …]
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| /linux/drivers/rtc/ |
| H A D | rtc-max6900.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 #define MAX6900_REG_SC 0 /* seconds 00-59 */
22 #define MAX6900_REG_MN 1 /* minutes 00-59 */
23 #define MAX6900_REG_HR 2 /* hours 00-23 */
24 #define MAX6900_REG_DT 3 /* day of month 00-31 */
25 #define MAX6900_REG_MO 4 /* month 01-12 */
26 #define MAX6900_REG_DW 5 /* day of week 1-7 */
27 #define MAX6900_REG_YR 6 /* year 00-99 */
35 #define MAX6900_REG_CT_WP (1 << 7) /* Write Protect */
38 * register read/write commands
[all …]
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| /linux/fs/jffs2/ |
| H A D | jffs2_fs_sb.h | 2 * JFFS2 -- Journalling Flash File System, Version 2.
4 * Copyright © 2001-2007 Red Hat, Inc.
5 * Copyright © 2004-2010 David Woodhouse <dwmw2@infradead.org>
39 * latter users to write to the file system if the amount if the
61 struct mutex alloc_sem; /* Used to protect all the following
62 fields, and also to protect against
63 out-of-order writing of nodes. And GC. */
81 uint8_t resv_blocks_write; /* ... allow a normal filesystem write */
96 struct jffs2_eraseblock *gcblock; /* The block we're currently garbage-collecting */
111 spinlock_t erase_completion_lock; /* Protect free_list and erasing_list
[all …]
|
| H A D | README.Locking | 3 ---------------------------
11 ---------
13 The alloc_sem is a per-filesystem mutex, used primarily to ensure
16 upon write completion (jffs2_complete_reservation()). Note that
19 preventing any other write activity on the file system during a
24 which they belong. This is for the benefit of NAND flash - adding new
26 until this happens we ensure that any data in the write-buffer at the
28 was written afterwards. Hence, we can ensure the newly-obsoleted nodes
29 don't actually get erased until the write-buffer has been flushed to
32 With the introduction of NAND flash support and the write-buffer,
[all …]
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| /linux/Documentation/admin-guide/mm/ |
| H A D | pagemap.rst | 12 physical frame each virtual page is mapped to. It contains one 64-bit
16 * Bits 0-54 page frame number (PFN) if present
17 * Bits 0-4 swap type if swapped
18 * Bits 5-54 swap offset if swapped
19 * Bit 55 pte is soft-dirty (see
20 Documentation/admin-guide/mm/soft-dirty.rst)
22 * Bit 57 pte is uffd-wp write-protected (since 5.13) (see
23 Documentation/admin-guide/mm/userfaultfd.rst)
25 * Bits 59-60 zero
26 * Bit 61 page is file-page or shared-anon (since 3.5)
[all …]
|
| H A D | userfaultfd.rst | 8 Userfaults allow the implementation of on-demand paging from userland
38 Vmas are not suitable for page- (or hugepage) granular fault tracking
48 is a corner case that would currently return ``-EBUSY``).
54 ----------------------
63 - Any user can always create a userfaultfd which traps userspace page faults
67 - In order to also trap kernel page faults for the address space, either the
84 --------------------------
101 - The ``UFFD_FEATURE_EVENT_*`` flags indicate that various other events
103 detail below in the `Non-cooperative userfaultfd`_ section.
105 - ``UFFD_FEATURE_MISSING_HUGETLBFS`` and ``UFFD_FEATURE_MISSING_SHMEM``
[all …]
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| /linux/drivers/target/ |
| H A D | target_core_sbc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (c) Copyright 2002-2013 Datera, Inc.
13 #include <linux/crc-t10dif.h>
14 #include <linux/t10-pi.h>
34 struct se_device *dev = cmd->se_dev; in sbc_emulate_readcapacity()
35 unsigned char *cdb = cmd->t_task_cdb; in sbc_emulate_readcapacity()
36 unsigned long long blocks_long = dev->transport->get_blocks(dev); in sbc_emulate_readcapacity()
42 * SBC-2 says: in sbc_emulate_readcapacity()
49 * In SBC-3, these fields are obsolete, but some SCSI in sbc_emulate_readcapacity()
51 * follow SBC-2. in sbc_emulate_readcapacity()
[all …]
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| /linux/include/linux/ |
| H A D | fsl_ifc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
35 * CSPR - Chip Select Property Register
47 /* Write Protect */
69 (__ilog2(n) - IFC_AMASK_SHIFT))
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
123 * Chip Select Option Register - NOR Flash Mode
150 * Chip Select Option Register - GPCM Mode
152 /* GPCM Mode - Normal */
[all …]
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| /linux/mm/ |
| H A D | mapping_dirty_helpers.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * struct wp_walk - Private struct for pagetable walk callbacks
25 * wp_pte - Write-protect a pte
31 * The function write-protect
[all...] |
| /linux/include/linux/clk/ |
| H A D | at91_pmc.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * Power Management Controller (PMC) - System peripherals registers.
55 #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
57 #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
69 #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
70 #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
186 #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
207 #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
219 #define AT91_PMC_LPM BIT(20) /* Low-power Mode */
229 #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
[all …]
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| /linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | nvmem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
23 "#address-cells":
26 "#size-cells":
29 read-only:
34 wp-gpios:
36 GPIO to which the write-protect pin of the chip is connected.
37 The write-protect GPIO is asserted, when it's driven high
[all …]
|
| /linux/drivers/scsi/ |
| H A D | pmcraid.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * pmcraid.h -- PMC Sierra MaxRAID controller driver header file
5 * Written By: Anil Ravindranath<anil_ravindranath@pmc-sierra.com>
6 * PMC-Sierra Inc
39 #define PMC_BIT8(n) (1 << (7-n))
40 #define PMC_BIT16(n) (1 << (15-n))
41 #define PMC_BIT32(n) (1 << (31-n))
58 /* MAX_IOADLS : max number of scatter-gather lists supported by IOA
197 /* structure to represent a scatter-gather element (IOADL descriptor) */
526 /* pmcraid_sglist - Scatter-gather list allocated for passthrough ioctls
[all …]
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| /linux/tools/laptop/freefall/ |
| H A D | freefall.c | 1 // SPDX-License-Identifier: GPL-2.0-only
32 return -EINVAL; in set_unload_heads_path()
33 strncpy(device_path, device, sizeof(device_path) - 1); in set_unload_heads_path()
35 snprintf(unload_heads_path, sizeof(unload_heads_path) - 1, in set_unload_heads_path()
65 if (write(fd, buf, strlen(buf)) != strlen(buf)) { in write_int()
66 perror("write"); in write_int()
80 static void protect(int seconds) in protect() function
102 protect(0); in ignore_me()
117 ret = -EINVAL; in main()
152 if ((ret == -1) && (errno == EINTR)) { in main()
[all …]
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| /linux/arch/m68k/include/asm/ |
| H A D | m53xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m53xxacr.h -- ColdFire version 3 core cache support
18 * configurable write-through or copy-back operation.
30 #define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
31 #define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
34 #define CACR_WPROTECT 0x00000020 /* Write protect*/
46 #define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
47 #define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
50 #define ACR_WPROTECT 0x00000004 /* Write protect region */
66 #define CACHE_WAYS 4 /* 4 ways - set associative */
[all …]
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| H A D | m54xxacr.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define CACR_DWP 0x40000000 /* Data write protection */
17 #define CACR_DDCM_WT 0x00000000 /* Write through cache*/
38 #define ACR_CM_WT 0x00000000 /* Write through mode */
43 #define ACR_SP 0x00000008 /* Supervisor protect */
44 #define ACR_WPROTECT 0x00000004 /* Write protect */
47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8)
51 #define ICACHE_SIZE 0x4000 /* instruction - 16k */
52 #define DCACHE_SIZE 0x2000 /* data - 8k */
56 #define ICACHE_SIZE 0x8000 /* instruction - 32k */
[all …]
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | arm,pl172.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
22 - compatible
27 - enum:
[all …]
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| /linux/include/xen/interface/ |
| H A D | features.h | 1 /* SPDX-License-Identifier: MIT */
14 * If set, the guest does not need to write-protect its pagetables, and can
20 * If set, the guest does not need to write-protect its segment descriptor
26 * If set, translation between the guest's 'pseudo-physical' address space
28 * mode the guest does not need to perform phys-to/from-machine translations
79 * must be located in lower 1MB, as required by ACPI Specification for IA-PC
87 * A direct-mapped (or 1:1 mapped) domain is a domain for which its
88 * local pages have gfn == mfn. If a domain is direct-mapped,
93 * - not auto_translated domains (x86 only) are always direct-mapped
94 * - on x86, auto_translated domains are not direct-mapped
[all …]
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| /linux/drivers/iio/dac/ |
| H A D | ti-dac7612.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * DAC7612 Dual, 12-Bit Serial input Digital-to-Analog Converter
8 * Licensed under the GPL-2.
26 * Lock to protect the state of the device from potential concurrent
27 * write accesses from userspace. The write operation requires an
28 * SPI write, then toggling of a GPIO, so the lock aims to protect
44 priv->data[0] = BIT(DAC7612_START) | (channel << DAC7612_ADDRESS); in dac7612_cmd_single()
45 priv->data[0] |= val >> 8; in dac7612_cmd_single()
46 priv->data[1] = val & 0xff; in dac7612_cmd_single()
48 priv->cache[channel] = val; in dac7612_cmd_single()
[all …]
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| /linux/arch/sh/boards/mach-kfr2r09/ |
| H A D | lcd_wqvga.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Register settings based on the out-of-tree t33fb.c driver
22 /* The on-board LCD module is a Hitachi TX07D34VM0AAA. This module is made
24 * communicating with the main port of the LCDC using an 18-bit SYS interface.
30 0x02, /* WEMODE: 1=cont, 0=one-shot */
62 return so->read_data(sohandle); in read_reg()
70 so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */ in write_reg()
72 so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */ in write_reg()
90 /* access protect OFF */ in read_device_code()
125 /* write start */ in clear_memory()
[all …]
|