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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Darm,pl172.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 - arm,pl172
19 - arm,pl175
20 - arm,pl176
22 - compatible
27 - enum:
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H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
25 8: Synchronous read synchronous write PSRAM.
26 9: Synchronous read asynchronous write PSRAM.
27 10: Synchronous read synchronous write NOR.
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H A Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
/linux/tools/testing/selftests/thermal/intel/workload_hint/
H A Dworkload_hint_test.c1 // SPDX-License-Identifier: GPL-2.0
35 perror("Unable to open workload type feature enable file"); in workload_hint_exit()
39 if (write(fd, "0\n", 2) < 0) { in workload_hint_exit()
55 int delay = 0; in main() local
57 printf("Usage: workload_hint_test [notification delay in milli seconds]\n"); in main()
60 ret = sscanf(argv[1], "%d", &delay); in main()
62 printf("Invalid delay\n"); in main()
66 printf("Setting notification delay t in main()
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/linux/drivers/iio/imu/
H A Dadis.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/delay.h>
27 * __adis_write_reg() - write N bytes to register (unlocked version)
30 * @value: The value to write to device (up to 4 bytes)
41 .tx_buf = adis->tx, in __adis_write_reg()
44 .delay.value = adis->data->write_delay, in __adis_write_reg()
45 .delay.unit = SPI_DELAY_UNIT_USECS, in __adis_write_reg()
47 .tx_buf = adis->tx + 2, in __adis_write_reg()
50 .delay.value = adis->data->write_delay, in __adis_write_reg()
[all …]
/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c1 // SPDX-License-Identifier: GPL-2.0
3 * ip22-nvram.c: NVRAM and serial EEPROM handling.
5 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
14 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
15 #define EEPROM_WRITE 0xa000 /* serial memory write */
16 #define EEPROM_WRALL 0x8800 /* write all registers */
19 #define EEPROM_PREN 0x9800 /* enable protect register mode */
21 #define EEPROM_PRWRITE 0xa000 /* write protect register */
24 #define EEPROM_EPROT 0x01 /* Protect register enable */
31 #define delay() ({ \ macro
[all …]
/linux/drivers/misc/eeprom/
H A Deeprom_93cx6.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2004 - 2006 rt2x00 SourceForge Project
14 #include <linux/delay.h>
24 eeprom->reg_data_clock = 1; in eeprom_93cx6_pulse_high()
25 eeprom->register_write(eeprom); in eeprom_93cx6_pulse_high()
28 * Add a short delay for the pulse to work. in eeprom_93cx6_pulse_high()
37 eeprom->reg_data_clock = 0; in eeprom_93cx6_pulse_low()
38 eeprom->register_write(eeprom); in eeprom_93cx6_pulse_low()
41 * Add a short delay for the pulse to work. in eeprom_93cx6_pulse_low()
51 * Clear all flags, and enable chip select. in eeprom_93cx6_startup()
[all …]
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
19 /* Enable bit for Inter module */
21 /* Enable bit for Sensor Interface module */
23 /* Enable bit for Host Burst Access */
25 /* Enable bit for Loop Filter module */
27 /* Enable bit for PLBK module */
[all …]
/linux/Documentation/accounting/
H A Ddelay-accounting.rst2 Delay accounting
9 The per-task delay accounting functionality measures
18 g) write-protect copy
29 delay statistics aggregated for all tasks (or threads) belonging to a
34 aggregate delay statistics into arbitrary groups. To enable this, delay
40 ---------
42 Delay accounting uses the taskstats interface which is described
44 generic data structure to userspace corresponding to per-pid and per-tgid
45 statistics. The delay accounting functionality populates specific fields of
50 for a description of the fields pertaining to delay accounting.
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dparam.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
15 #define OPTION_UNSET -1
36 /* Transmit Interrupt Delay in units of 1.024 microseconds
37 * Tx interrupt delay needs to typically be set to something non-zero
39 * Valid Range: 0-65535
41 E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
46 /* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
48 * Valid Range: 0-65535
50 E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
[all …]
/linux/lib/
H A DKconfig.kcsan1 # SPDX-License-Identifier: GPL-2.0-only
7 def_bool (CC_IS_CLANG && $(cc-option,-fsanitize=thread -mllvm -tsan-distinguish-volatil
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/linux/include/soc/at91/
H A Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
51 #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
52 #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
54 #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
55 #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
59 #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
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/linux/drivers/mmc/host/
H A Dsdhci-bcm-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/delay.h>
14 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
63 return -EFAULT; in sdhci_bcm_kona_sd_reset()
72 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
73 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
74 * is very low w.r.t AHB clock, mainly during boot-time and during card in sdhci_bcm_kona_sd_reset()
75 * insert-removal. in sdhci_bcm_kona_sd_reset()
87 /* enable the interrupt from the IP core */ in sdhci_bcm_kona_sd_init()
[all …]
/linux/Documentation/driver-api/media/drivers/
H A Dradiotrack.rst1 .. SPDX-License-Identifier: GPL-2.0
11 ----------------
24 ------------------
26 I have a RadioTrack card from back when I ran an MS-Windows platform. After
27 converting to Linux, I found Gideon le Grange's command-line software for
29 comfortable X-windows interface, and added a scanning feature. For hack
32 broadcast TV channels, situated just below and above the 87.0-109.0 MHz range.
36 So, without further delay, here are the details.
40 --------------------
42 The RadioTrack card is an ISA 8-bit FM radio card. The radio frequency (RF)
[all …]
/linux/drivers/net/ethernet/realtek/
H A Datp.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 ushort rx_status; /* Unknown bit assignments :-<. */
29 #define WrAddr 0x40 /* Set address of EPLC read, write register. */
60 #define CMR1h_RxENABLE 0x02 /* Rx unit enable. */
61 #define CMR1h_TxENABLE 0x01 /* Tx unit enable. */
66 #define CMR1_BufEnb 0x01 /* Enable the buffer(?). */
67 #define CMR1_NextPkt 0x01 /* Enable the buffer(?). */
99 inbyte(port + PAR_STATUS); /* Settling time delay */ in read_nibble()
116 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ in read_byte_mode0()
117 inbyte(ioaddr + PAR_STATUS); /* Settling time delay -- needed! */ in read_byte_mode0()
[all …]
/linux/arch/arm/include/asm/hardware/
H A Dlocomo.h38 #define LOCOMO_ASD 0x20 /* AD start delay */
39 #define LOCOMO_HSD 0x28 /* HSYS delay */
53 #define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */
63 #define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
67 #define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
68 #define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
70 #define LOCOMO_SPITD 0x20 /* SPI transfer data write */
77 #define LOCOMO_GPE 0x94 /* GPIO input enable */
83 #define LOCOMO_GWE 0xac /* GPIO status write enable */
84 #define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */
[all …]
/linux/drivers/hid/intel-thc-hid/intel-thc/
H A Dintel-thc-dev.c1 /* SPDX-License-Identifier: GPL-2.0 */
9 #include "intel-thc-dev.h"
10 #include "intel-thc-hw.h"
16 void __iomem *base = thc_ctx->mmio_addr; in thc_regmap_read()
26 void __iomem *base = thc_ctx->mmio_addr; in thc_regmap_write()
58 * thc_clear_state - Clear THC hardware state
71 regmap_write_bits(dev->thc_regmap, THC_M_PRT_ERR_CAUSE_OFFSET, val, val); in thc_clear_state()
74 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_1_OFFSET, in thc_clear_state()
77 regmap_write_bits(dev->thc_regmap, THC_M_PRT_READ_DMA_CNTRL_2_OFFSET, in thc_clear_state()
81 regmap_write_bits(dev->thc_regmap, THC_M_PRT_INT_STATUS_OFFSET, in thc_clear_state()
[all …]
H A Dintel-thc-dev.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "intel-thc-dma.h"
12 #include "intel-thc-wot.h"
29 * @THC_NONDMA_INT: THC non-DMA interrupt
53 * struct thc_device - THC private device struct
60 * @wot: THC Wake-on-Touch data
61 * @write_complete_wait: Signal event for DMA write complete
63 * @write_done: Bool value that indicates if DMA write is done
65 * @perf_limit: The delay between read operation and write operation
66 * @i2c_subip_regs: The copy of THC I2C sub-system registers for resuming restore
[all …]
/linux/drivers/rtc/
H A Drtc-max77686.c1 // SPDX-License-Identifier: GPL-2.0+
7 // based on rtc-max8997.c
12 #include <linux/delay.h>
16 #include <linux/mfd/max77686-private.h>
23 #define MAX77686_INVALID_I2C_ADDR (-1)
26 #define MAX77686_INVALID_REG (-1)
38 /* RTC Alarm Enable */
45 * MAX77802 has separate register (RTCAE1) for alarm enable instead
63 * struct max77686_rtc_driver_data - model-specific configuration
64 * @delay: Minimum usecs needed for a RTC update
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
[all …]
/linux/drivers/memory/
H A Dpl172.c1 // SPDX-License-Identifier: GPL-2.0
9 * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
65 cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start; in pl172_timing_prop()
69 dev_err(&adev->dev, "%s timing too tight\n", name); in pl172_timing_prop()
70 return -EINVAL; in pl172_timing_prop()
73 writel(cycles, pl172->base + reg_offset); in pl172_timing_prop()
76 dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start + in pl172_timing_prop()
77 readl(pl172->base + reg_offset)); in pl172_timing_prop()
90 if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) { in pl172_setup_static()
98 dev_err(&adev->dev, "invalid memory width cs%u\n", cs); in pl172_setup_static()
[all …]
/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192d/
H A Dfw_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
18 void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable) in rtl92d_enable_fw_download() argument
23 if (enable) { in rtl92d_enable_fw_download()
35 * so don't write this reg here in rtl92d_enable_fw_download()
53 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) in rtl92d_write_fw()
90 return -EIO; in rtl92d_fw_free_to_go()
108 u8 delay = 100; in rtl92d_firmware_selfreset() local
110 if (rtlhal->interface == INTF_USB) { in rtl92d_firmware_selfreset()
111 delay *= RTL_USB_DELAY_FACTOR; in rtl92d_firmware_selfreset()
[all …]
/linux/drivers/net/dsa/qca/
H A Dqca8k-8xxx.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
47 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_mii_write_lo()
49 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_lo()
50 "failed to write qca8k 32bit lo register\n"); in qca8k_mii_write_lo()
62 ret = bus->write(bus, phy_id, regnum, hi); in qca8k_mii_write_hi()
64 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_hi()
65 "failed to write qca8k 32bit hi register\n"); in qca8k_mii_write_hi()
75 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_lo()
83 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_lo()
[all …]
/linux/drivers/reset/
H A Dreset-k230.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
4 * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
16 * unambiguously signal whether hardware reset removal or clock-stop period
21 …* https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87…
25 #include <linux/delay.h>
30 #include <linux/reset-controller.h>
33 #include <dt-bindings/reset/canaan,k230-rst.h>
36 * enum k230_rst_type - K230 reset types
38 * Automatically clears, has write enable and done bit, active high
[all …]

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