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/linux/sound/hda/core/
H A Dcontroller.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio controller helpers
19 for (timeout = 1000; timeout > 0; timeout--) { in azx_clear_corbrp()
25 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n", in azx_clear_corbrp()
29 for (timeout = 1000; timeout > 0; timeout- in azx_clear_corbrp()
229 unsigned int wp, rp; snd_hdac_bus_send_cmd_corb() local
272 unsigned int rp, wp; snd_hdac_bus_update_rirb() local
[all...]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC Controller & Slots Common Properties
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 possible slots or ports for multi-slot controllers.
17 "#address-cells":
22 "#size-cells":
29 broken-cd:
[all …]
H A Dk3-dw-mshc.txt2 Storage Host Controller
4 Read synopsys-dw-mshc.txt for more details
6 The Synopsys designware mobile storage host controller is used to interface
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
10 extensions to the Synopsys Designware Mobile Storage Host Controller.
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
[all …]
H A Dsunplus,mmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus MMC Controller
11 - Tony Huang <tonyhuang.sunplus@gmail.com>
12 - Li-hao Kuo <lhjeff911@gmail.com>
15 - $ref: mmc-controller.yaml
20 - sunplus,sp7021-mmc
35 - compatible
36 - reg
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
17 registers and for its data input/output buffer. On some SoCs, this controller
[all …]
H A Dnvidia-tegra20-nand.txt1 NVIDIA Tegra NAND Flash controller
4 - compatible: Must be one of:
5 - "nvidia,tegra20-nand"
6 - reg: MMIO address range
7 - interrupts: interrupt output of the NFC controller
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clocks/clock-bindings.txt for details.
10 - clock-names: Must include the following entries:
11 - nand
12 - resets: Must contain an entry for each entry in reset-names.
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
35 mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50-kobo-aura.dts1 // SPDX-License-Identifier: GPL-2.0+
4 // The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B.
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
16 stdout-path = "serial1:115200n8";
24 gpio-leds {
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_leds>;
[all …]
H A Dimx6ul-tx6ul-0011.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6ul-tx6ul.dtsi"
11 model = "Ka-Ro electronics TXUL-0011 Module";
12 compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_usdhc2>;
27 bus-width = <4>;
28 no-1-8-v;
[all …]
H A Dimx6sx-sabreauto.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
11 compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_led>;
23 led-user {
26 linux,default-trigger = "heartbeat";
30 vcc_sd3: regulator-vcc-sd3 {
31 compatible = "regulator-fixed";
[all …]
H A Dimx6dl-tx6u-8033.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6qdl-tx6.dtsi"
9 #include "imx6qdl-tx6-lcd.dtsi"
12 model = "Ka-Ro electronics TX6U-8033 Module";
13 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_usdhc4>;
27 bus-width = <4>;
[all …]
H A Dimx6dl-tx6s-8035.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2015-2017 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6qdl-tx6.dtsi"
9 #include "imx6qdl-tx6-lcd.dtsi"
12 model = "Ka-Ro electronics TX6S-8035 Module";
13 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
16 /delete-node/ cpu@1;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_usdhc4>;
[all …]
H A Dimx6q-tx6q-1036.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6qdl-tx6.dtsi"
9 #include "imx6qdl-tx6-lcd.dtsi"
12 model = "Ka-Ro electronics TX6Q-1036 Module";
13 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_usdhc4>;
31 bus-width = <4>;
[all …]
H A Dimx6q-tx6q-1020.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2014-2017 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6qdl-tx6.dtsi"
9 #include "imx6qdl-tx6-lcd.dtsi"
12 model = "Ka-Ro electronics TX6Q-1020 Module";
13 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_usdhc4>;
31 bus-width = <4>;
[all …]
H A Dimx6qp-tx6qp-8137.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6qdl-tx6.dtsi"
9 #include "imx6qdl-tx6-lvds.dtsi"
12 model = "Ka-Ro electronics TX6QP-8137 Module";
13 compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_usdhc4>;
35 bus-width = <4>;
[all …]
H A Dimx6qp-tx6qp-8037.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
3 * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
6 /dts-v1/;
8 #include "imx6qdl-tx6.dtsi"
9 #include "imx6qdl-tx6-lcd.dtsi"
12 model = "Ka-Ro electronics TX6QP-8037 Module";
13 compatible = "karo,imx6qp-tx6qp", "fsl,imx6qp";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_usdhc4>;
31 bus-width = <4>;
[all …]
/linux/sound/pci/lola/
H A Dlola.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for Digigram Lola PCI-e boards
11 #include <linux/dma-mapping.h>
34 /* Lola-specific options */
40 [0 ... (SNDRV_CARDS - 1)] = LOLA_GRANULARITY_MAX
45 [0 ... (SNDRV_CARDS -
88 unsigned int wp = chip->corb.wp + 1; corb_send_verb() local
111 unsigned int rp, wp; lola_update_rirb() local
[all...]
/linux/drivers/bus/mhi/host/
H A Ddebugfs.c1 // SPDX-License-Identifier: GPL-2.0
18 struct mhi_controller *mhi_cntrl = m->private; in mhi_debugfs_states_show()
22 to_mhi_pm_state_str(mhi_cntrl->pm_state), in mhi_debugfs_states_show()
24 mhi_state_str(mhi_cntrl->dev_state), in mhi_debugfs_states_show()
25 TO_MHI_EXEC_STR(mhi_cntrl->ee), in mhi_debugfs_states_show()
26 str_true_false(mhi_cntrl->wake_set)); in mhi_debugfs_states_show()
29 seq_printf(m, "M0: %u M2: %u M3: %u", mhi_cntrl->M0, mhi_cntrl->M2, in mhi_debugfs_states_show()
30 mhi_cntrl->M3); in mhi_debugfs_states_show()
33 atomic_read(&mhi_cntrl->dev_wake), in mhi_debugfs_states_show()
34 atomic_read(&mhi_cntrl->pending_pkts)); in mhi_debugfs_states_show()
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-pogoplug-series-4.dts1 // SPDX-License-Identifier: GPL-2.0
3 * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4
10 /dts-v1/;
13 #include "kirkwood-6192.dtsi"
14 #include <dt-bindings/input/linux-event-codes.h>
18 compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192",
27 stdout-path = "uart0:115200n8";
31 compatible = "gpio-keys";
32 pinctrl-0 = <&pmx_button_eject>;
33 pinctrl-names = "default";
[all …]
/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1-nezha.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
7 * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed
8 * directly to pads on the SoC, others come from an 8-bit pcf857x IO
10 * one set for the pcf857x, and one set for the pio controller.
12 * Lines which are routed to the 40-pin header are named as follows:
15 * <pin#> is the actual pin number of the 40-pin header
20 * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf
23 #include <dt-bindings/gpio/gpio.h>
24 #include <dt-bindings/input/input.h>
[all …]
/linux/arch/powerpc/boot/dts/
H A Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
[all …]
/linux/Documentation/devicetree/bindings/iio/chemical/
H A Dsciosense,ens160.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ScioSense ENS160 multi-gas sensor
10 - Gustavo Silva <gustavograzs@gmail.com>
13 Digital Multi-Gas Sensor for Monitoring Indoor Air Quality.
16 https://www.sciosense.com/wp-content/uploads/2023/12/ENS160-Datasheet.pdf
21 - sciosense,ens160
29 vdd-supply: true
30 vddio-supply: true
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-khadas-vim3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/gpio/meson-g12a-gpio.h>
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
22 stdout-path = "serial0:115200n8";
30 adc-keys {
31 compatible = "adc-keys";
32 io-channels = <&saradc 2>;
33 io-channel-names = "buttons";
[all …]
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8-fernsehfee3.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/leds/common.h>
27 stdout-path = "serial0:115200n8";
35 gpio-keys {
36 compatible = "gpio-keys-polled";
37 poll-interval = <100>;
39 power-button {
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9m10g45ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
8 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
13 model = "Atmel AT91SAM9M10G45-EK";
18 stdout-path = "serial0:115200n8";
27 clock-frequency = <32768>;
31 clock-frequency = <12000000>;
43 compatible = "atmel,tcb-timer";
48 compatible = "atmel,tcb-timer";
[all …]

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