/linux/drivers/w1/masters/ |
H A D | Kconfig | 3 # 1-wire bus master configuration 6 menu "1-wire Bus Masters" 9 tristate "AMD AXI 1-wire bus host" 11 Say Y here is you want to support the AMD AXI 1-wire IP core. 13 correctly timed 1 wire transactions without relying on GPIO timing 20 tristate "Matrox G400 transport layer for 1-wire" 23 Say Y here if you want to communicate with your 1-wire devices 30 tristate "DS2490 USB <-> W1 transport layer for 1-wire" 40 tristate "Maxim DS2482 I2C to 1-Wire bridge" 44 I2C to 1-Wire bridge. [all …]
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H A D | w1-uart.c | 3 * w1-uart - UART 1-Wire bus driver 5 * Uses the UART interface (via Serial Device Bus) to create the 1-Wire 6 * timing patterns. Implements the following 1-Wire master interface: 31 * struct w1_uart_config - configuration for 1-Wire operation 33 * @delay_us: delay to complete a 1-Wire cycle (in us) 34 * @tx_byte: byte to generate 1-Wire timing pattern 43 * struct w1_uart_device - 1-Wire UART device structure 46 * @cfg_reset: config for 1-Wire reset 47 * @cfg_touch_0: config for 1-Wire write-0 cycle 48 * @cfg_touch_1: config for 1-Wire write-1 and read cycle [all …]
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H A D | amd_axi_w1.c | 3 * amd_axi_w1 - AMD 1Wire programmable logic bus host driver 23 /* 1-wire AMD IP definition */ 113 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_touch_bit() 161 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_read_byte() 202 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_write_byte() 240 /* Reset 1-wire Axi IP */ in amd_axi_w1_reset_bus() 243 /* Wait for READY signal to be 1 to ensure 1-wire IP is ready */ in amd_axi_w1_reset_bus() 272 /* Reset the 1-wire AXI IP. Put the IP in reset state and clear registers */ 329 dev_err(dev, "AMD 1-wire IP not detected in hardware\n"); in amd_axi_w1_probe() 379 { .compatible = "amd,axi-1wire-host" }, [all …]
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H A D | ds2482.c | 7 * It is a I2C to 1-wire bridge. 8 * There are two variations: -100 and -800, which have 1 or 8 1-wire ports. 28 * a 1-Wire line from low to high. When APU = 0, active pullup is disabled 30 * only a single slave on the 1-Wire line. 70 #define DS2482_REG_CFG_1WS 0x08 /* 1-wire speed */ 113 /* 1-wire interface(s) */ 200 * 1-Wire interface code 206 * ds2482_wait_1wire_idle - Waits until the 1-wire interface is idle (not busy) 232 * The 1-wire interface must be idle before calling this function. 379 * ds2482_w1_reset_bus - Sends a reset on the 1-wire interfac [all...] |
H A D | sgi_w1.c | 3 * sgi_w1.c - w1 master driver for one wire support in SGI ASICs 41 * reset the device on the One Wire interface 56 * this is the low level routine to read/write a bit on the One Wire 126 MODULE_DESCRIPTION("Driver for One-Wire IP in SGI ASICs");
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/linux/drivers/w1/slaves/ |
H A D | Kconfig | 3 # 1-wire slaves configuration 6 menu "1-wire Slaves" 11 Say Y here if you want to connect 1-wire thermal sensors to your 12 wire. 17 Say Y here if you want to connect 1-wire 18 simple 64bit memory rom(ds2401/ds2411/ds1990*) to your wire. 23 Say Y or M here if you want to use a DS2405 1-wire 31 Say Y here if you want to use a 1-wire 47 Say Y here if you want to use a 1-wire 54 Say Y or M here if you want to use a 1-wire [all …]
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/linux/Documentation/w1/masters/ |
H A D | w1-uart.rst | 13 UART 1-Wire bus driver. The driver utilizes the UART interface via the 14 Serial Device Bus to create the 1-Wire timing patterns as described in 15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_. 17 …ing a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a… 22 1-Wire read bit, write bit or reset pulse. 24 For instance the timing pattern for a 1-Wire reset and presence detect uses 27 for 1-Wire to 521 us. A present 1-Wire device changes the received byte by 29 the 1-Wire operation. 31 Similar for a 1-Wire read bit or write bit, which uses the baud-rate 37 a 1-Wire read or write operation 115200. In case the actual baud-rate [all …]
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H A D | omap-hdq.rst | 2 Kernel driver for omap HDQ/1-wire module 7 HDQ/1-wire controller on the TI OMAP 2430/3430 platforms. 15 The HDQ/1-Wire module of TI OMAP2430/3430 platforms implement the hardware 17 Semiconductor 1-Wire protocols. These protocols use a single wire for 18 communication between the master (HDQ/1-Wire controller) and the slave 19 (HDQ/1-Wire external compliant device). 21 A typical application of the HDQ/1-Wire module is the communication with battery 24 The controller supports operation in both HDQ and 1-wire mode. The essential 25 difference between the HDQ and 1-wire mode is how the slave device responds to 29 does not respond with a presence pulse as it does in the 1-Wire protocol. [all …]
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/linux/Documentation/devicetree/bindings/w1/ |
H A D | w1-uart.yaml | 7 title: UART 1-Wire Bus 13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus 14 to create the 1-Wire timing patterns. 18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit, 22 a 1-Wire read or write operation 115200. In case the actual baud-rate 24 to generate the 1-Wire timing patterns. 26 https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html 35 The baud rate for the 1-Wire reset and presence detect. 40 The baud rate for the 1-Wire write-0 cycle. 45 The baud rate for the 1-Wire write-1 and read cycle.
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H A D | amd,axi-1wire-host.yaml | 4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml# 7 title: AMD AXI 1-wire bus host for programmable logic 14 const: amd,axi-1wire-host 38 compatible = "amd,axi-1wire-host";
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/linux/include/linux/mfd/ |
H A D | motorola-cpcap.h | 186 #define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */ 212 #define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */ 213 #define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */ 214 #define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */ 215 #define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */ 217 #define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */ 219 #define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */ 220 #define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */ 221 #define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */ 222 #define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */ [all …]
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/linux/Documentation/peci/ |
H A D | peci.rst | 24 PECI Wire 27 PECI Wire interface uses a single wire for self-clocking and data 29 physical layer is a self-clocked one-wire bus signal that begins each 32 value is logic '0' or logic '1'. PECI Wire also includes variable data 35 For PECI Wire, each processor package will utilize unique, fixed
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/linux/Documentation/iio/ |
H A D | ad4000.rst | 35 CS mode, 3-wire turbo mode 38 Datasheet "3-wire" mode is what most resembles standard SPI connection which, 41 "CS Mode, 3-Wire Turbo Mode" connection in datasheets. 42 NOTE: The datasheet definition of 3-wire mode for the AD4000 series is NOT the 43 same of standard spi-3wire mode. 65 CS mode, 3-wire, without busy indicator 68 Another wiring configuration supported as "3-wire" mode has the SDI pin 71 is not possible. This connection mode saves one wire and works with any SPI 107 CS mode, 4-wire without busy indicator 110 In datasheet "4-wire" mode, the controller CS line is connected to the ADC SDI
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/linux/Documentation/devicetree/bindings/iio/temperature/ |
H A D | maxim,max31865.yaml | 22 maxim,3-wire: 25 enables 3-wire RTD connection. Else 2-wire or 4-wire RTD connection. 51 maxim,3-wire;
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/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | intel,ce4100-lapic.yaml | 42 intel,virtual-wire-mode: 47 Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. 52 mode is configured to virtual wire compatibility mode. 70 intel,virtual-wire-mode;
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/linux/arch/sh/mm/ |
H A D | tlb-urb.c | 18 * Load the entry for 'addr' into the TLB and wire the entry. 32 * Make sure we're not trying to wire the last TLB entry slot. in tlb_wire_entry() 49 /* ... and wire it up. */ in tlb_wire_entry() 64 * It should also be noted that it is not possible to wire and unwire 65 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
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/linux/Documentation/devicetree/bindings/display/panel/ |
H A D | tpo,tpg110.yaml | 17 and other properties, and has a control interface over 3WIRE 39 protocol is not I2C but 3WIRE SPI. 62 spi-3wire: true 73 - spi-3wire 88 spi-3wire;
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/linux/arch/sh/include/mach-common/mach/ |
H A D | highlander.h | 62 #define PA_SMCR (PA_BCR+0x0600) /* 2-wire Serial control */ 63 #define PA_SMSMADR (PA_BCR+0x0602) /* 2-wire Serial Slave control */ 64 #define PA_SMMR (PA_BCR+0x0604) /* 2-wire Serial Mode control */ 65 #define PA_SMSADR1 (PA_BCR+0x0606) /* 2-wire Serial Address1 control */ 66 #define PA_SMTRDR1 (PA_BCR+0x0646) /* 2-wire Serial Data1 control */ 114 #define PA_SMCR (PA_BCR+0x0500) /* 2-wire Serial control */ 115 #define PA_SMSMADR (PA_BCR+0x0502) /* 2-wire Serial Slave control */ 116 #define PA_SMMR (PA_BCR+0x0504) /* 2-wire Serial Mode control */ 117 #define PA_SMSADR1 (PA_BCR+0x0506) /* 2-wire Serial Address1 control */ 118 #define PA_SMTRDR1 (PA_BCR+0x0546) /* 2-wire Serial Data1 control */
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/linux/drivers/w1/ |
H A D | Makefile | 3 # Makefile for the Dallas's 1-wire bus. 6 obj-$(CONFIG_W1) += wire.o 7 wire-objs := w1.o w1_int.o w1_family.o w1_netlink.o w1_io.o
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H A D | Kconfig | 3 tristate "Dallas's 1-wire support" 6 Dallas' 1-wire bus is useful to connect slow 1-pin devices 12 will be called wire.
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/linux/Documentation/devicetree/bindings/input/touchscreen/ |
H A D | ti,am3359-tsc.yaml | 17 description: Wires refer to application modes i.e. 4/5/8 wire touchscreen 36 ti,wire-config: 63 - ti,wire-config 74 ti,wire-config = <0x00 0x11 0x22 0x33>;
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/linux/drivers/iio/common/st_sensors/ |
H A D | st_sensors_spi.c | 33 * st_sensors_is_spi_3_wire() - check if SPI 3-wire mode has been selected 36 * Return: true if SPI 3-wire mode is selected, false otherwise. 43 if (device_property_read_bool(dev, "spi-3wire")) in st_sensors_is_spi_3_wire() 54 * st_sensors_configure_spi_3_wire() - configure SPI 3-wire if needed
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/linux/sound/ppc/ |
H A D | snd_ps3_reg.h | 39 * three wire serial 130 /* 3 Wire Audio Serial Output Channel Mutes (0..3) */ 142 /* All 3 Wire Serial Outputs Mute */ 180 3 Wire Audio Serial Outputs Buffer Read/Write 191 3 Wire Audio Serial Output Channel Buffer Read Numbers 193 Controller of 3 Wire Audio Serial Output Channels 203 3 Wire Audio Serial Output Channel Buffer Write Numbers 230 All 3-Wire Audio Serial Outputs Interrupt Mode 232 condition of all 3-wire Audio Serial Outputs. 267 3 Wire Audio Serial Output Channel Buffer Underflow [all …]
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/linux/Documentation/devicetree/bindings/sound/ |
H A D | awinic,aw8738.yaml | 14 (set using one-wire pulse control). The mode configures the speaker-guard 26 GPIO used for one-wire pulse control. The pin is typically called SHDN 32 description: Operation mode (number of pulses for one-wire pulse control)
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/linux/Documentation/devicetree/bindings/spi/ |
H A D | icpdas-lp8841-spi-rtc.txt | 28 - spi-3wire: The master itself has only 3 wire. It cannor work in 50 spi-3wire;
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