1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Cix Sky1 Soc Pin Controller 8 9maintainers: 10 - Gary Yang <gary.yang@cixtech.com> 11 12description: 13 The pin-controller is used to control Soc pins. There are two pin-controllers 14 on Cix Sky1 platform. one is used under S0 state, the other one is used under 15 S0 and S5 state. 16 17properties: 18 compatible: 19 enum: 20 - cix,sky1-pinctrl 21 - cix,sky1-pinctrl-s5 22 23 reg: 24 items: 25 - description: gpio base 26 27patternProperties: 28 '-cfg$': 29 type: object 30 additionalProperties: false 31 32 description: 33 A pinctrl node should contain at least one subnode representing the 34 pinctrl groups available on the machine. 35 36 patternProperties: 37 'pins$': 38 type: object 39 additionalProperties: false 40 41 description: 42 Each subnode will list the pins it needs, and how they should 43 be configured, with regard to muxer configuration, bias pull, 44 and drive strength. 45 46 allOf: 47 - $ref: pincfg-node.yaml# 48 - $ref: pinmux-node.yaml# 49 50 properties: 51 pinmux: 52 description: 53 Values are constructed from pin number and mux setting, pin 54 number is left shifted by 8 bits, then ORed with mux setting 55 56 bias-disable: true 57 58 bias-pull-up: true 59 60 bias-pull-down: true 61 62 drive-strength: 63 description: 64 typical current when output high level. 65 enum: [ 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 17, 18, 20, 21, 23, 66 24 ] 67 68 required: 69 - pinmux 70 71required: 72 - compatible 73 - reg 74 75additionalProperties: false 76 77examples: 78 - | 79 #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0) 80 pinctrl@4170000 { 81 compatible = "cix,sky1-pinctrl"; 82 reg = <0x4170000 0x1000>; 83 84 wifi_vbat_gpio: wifi-vbat-gpio-cfg { 85 pins { 86 pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>; 87 bias-pull-up; 88 drive-strength = <8>; 89 }; 90 }; 91 }; 92