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/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	memory.json	31 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 59 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 64 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 70 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 75 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied … 81 …"PublicDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied… [all …]
H A D	cache.json	279 "BriefDescription": "Counts the number of memory uops retired that were splits.", 285 …"PublicDescription": "Counts the number of memory uops retired that were splits. Available PDIST c… 312 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", 318 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache. Available PDIST co… 323 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 329 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 334 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 340 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 345 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 351 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… [all …]
H A D	pipeline.json	307 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 311 …were not consumed by the backend because allocation is stalled due to a mispredicted jump or a mac… 316 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 324 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 332 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 349 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by … 356 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 364 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 372 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 380 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	memory.json	31 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 37 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 42 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 48 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 53 "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", 59 …"PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIS… 64 "BriefDescription": "Counts all code reads that were supplied by DRAM.", 70 …"PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: … 75 …"BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied … 81 …"PublicDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied… [all …]
H A D	cache.json	279 "BriefDescription": "Counts the number of memory uops retired that were splits.", 285 …"PublicDescription": "Counts the number of memory uops retired that were splits. Available PDIST c… 312 "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", 318 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache. Available PDIST co… 323 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 329 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 334 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 340 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… 345 …"BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was se… 351 …"PublicDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was s… [all …]
H A D	pipeline.json	307 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 311 …were not consumed by the backend because allocation is stalled due to a mispredicted jump or a mac… 316 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 324 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 332 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 349 …"BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by … 356 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 364 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 372 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… 380 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A D	memory.json	117 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 123 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0", 128 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 134 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0", 139 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 145 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0", 150 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 156 "PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0", 161 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", 167 "PublicDescription": "Counts demand data reads that were no [all...]
H A D	adln-metrics.json	74 …"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to… 82 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 89 …"PublicDescription": "Counts the total number of issue slots that were not consumed by the backend… 93 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 100 …were not consumed by the backend because allocation is stalled due to a mispredicted jump or a mac… 104 …"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due … 109 …"PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due… 113 …"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to… 122 …"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due … 130 …"BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due … [all …]
H A D	cache.json	378 "BriefDescription": "Counts the number of memory uops retired that were splits.", 463 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.", 469 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache. Available PDIST counters: 0", 474 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", 480 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. Available PDIST counters: 0", 485 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", 491 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. Available PDIST counters: 0", 496 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", 502 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. Available PDIST counters: 0", 518 "BriefDescription": "Counts demand data reads that were supplie [all...]
H A D	pipeline.json	543 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", 547 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", 551 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", 559 "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", 567 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", 575 "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", 583 "BriefDescription": "Counts the total number of issue slots every cycle that were no [all...]
/linux/tools/perf/pmu-events/arch/x86/emeraldrapids/
H A D	memory.json	177 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 183 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. A… 188 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 194 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 199 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 205 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 210 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on… 216 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on… 221 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 227 …"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counter… [all …]
H A D	cache.json	180 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", 198 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", 216 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", 287 "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.", 313 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", 322 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", 479 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 484 "PublicDescription": "Counts retired load instructions whose data sources were Hit [all...]
/linux/tools/perf/pmu-events/arch/x86/sapphirerapids/
H A D	memory.json	177 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 183 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. A… 188 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 194 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 199 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 205 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 210 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on… 216 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on… 221 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 227 …"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counter… [all …]
H A D	cache.json	180 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", 198 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", 216 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", 287 "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.", 313 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", 322 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", 488 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 493 "PublicDescription": "Counts retired load instructions whose data sources were Hit [all...]
/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A D	memory.json	117 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 127 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 137 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 147 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 157 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on… 167 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 177 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,… 187 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,… 197 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, … 207 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke… [all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A D	memory.json	318 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 324 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. A… 330 …ction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache and were … 336 …ction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache and were … 342 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 348 …"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counter… 354 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 360 …"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counter… 366 …"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache and were supp… 372 …"PublicDescription": "Counts demand data reads that were not supplied by the L3 cache and were sup… [all …]
/linux/tools/perf/pmu-events/arch/x86/graniterapids/
H A D	memory.json	198 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 204 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. A… 209 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 215 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the… 220 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 226 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at… 231 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 237 …"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counter… 242 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,… 248 …"PublicDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2… [all …]
H A D	cache.json	108 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", 126 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", 144 "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", 215 "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.", 241 "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", 250 "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", 451 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", 456 "PublicDescription": "Counts retired load instructions whose data sources were Hit [all...]
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	memory.json	321 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", 327 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0", 333 "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", 339 "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0", 345 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 351 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0", 357 "BriefDescription": "Counts demand data reads that were supplied by DRAM.", 363 "PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0", 369 "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", 375 "PublicDescription": "Counts demand data reads that were no [all...]
/linux/Documentation/userspace-api/media/v4l/
H A D	hist-v4l2.rst	29 aliases ``O_NONCAP`` and ``O_NOIO`` were defined. Applications can set 40 struct ``video_standard`` and the color subcarrier fields were 59 module. The ``YUV422`` and ``YUV411`` planar image formats were added. 62 output devices were added. 110 Version 0.20 introduced a number of changes which were *not backward 115 1. Some typos in ``V4L2_FMT_FLAG`` symbols were fixed. struct v4l2_clip 137 4. All the different get- and set-format commands were swept into one 152 ``VIDIOC_S_PARM`` ioctls were merged with ``VIDIOC_G_OUTPARM`` and 159 6. Control enumeration was simplified, and two new control flags were 188 cause errors if it were being used for timestamping a multimedia [all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	pipeline.json	509 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", 513 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", 517 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]", 521 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younge [all...]
H A D	frontend.json	12 …"BriefDescription": "Counts the number of instructions retired that were tagged with having preced… 35 …"BriefDescription": "Counts the number of instructions retired that were tagged following an ms fl… 39 …"PublicDescription": "Counts the number of instructions retired that were tagged following an ms … 44 …"BriefDescription": "Counts the number of instructions retired that were tagged every cycle the de… 52 …tion": "Counts the number of instructions retired that were tagged because empty issue slots were … 60 …tion": "Counts the number of instructions retired that were tagged because empty issue slots were …
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	pipeline.json	360 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", 364 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", 368 "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]", 372 "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younge [all...]
/linux/Documentation/networking/device_drivers/ethernet/altera/
H A D	altera_tse.rst	14 driver were built for a Cyclone(R) V SOC FPGA board, a Cyclone(R) V FPGA board, 26 Quartus toolchain. Quartus 13.1 and 14.0 were used to build the design that 201 statistic is a count of the number of packets received that were not addressed 205 statistic is a count of the number of packets received that were addressed to 209 statistic is a count of the number of packets received that were addressed to 218 statistic counts the number of packets transmitted that were not addressed to 222 statistic counts the number of packets transmitted that were addressed to a 226 statistic counts the number of packets transmitted that were addressed to a 250 This statistic counts the total number of packets received that were 64 octets 254 2819. This statistic counts the total number of packets received that were [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen6/
H A D	execution.json	20 "BriefDescription": "Retired branch instructions that were mispredicted." 30 "BriefDescription": "Retired taken branch instructions that were mispredicted." 45 …"BriefDescription": "Retired near returns that were mispredicted. Each misprediction incurs the sa… 50 …"BriefDescription": "Retired indirect branch instructions that were mispredicted (only EX mispredi… 115 …"BriefDescription": "Retired conditional branch instructions that were mispredicted due to directi… 120 …"BriefDescription": "Retired unconditional indirect near branch instructions that were mispredicte… 148 …"BriefDescription": "Execution IBS tagged ops that retired but were discarded due to IBS filtering… 183 …"BriefDescription": "Memory Profiler IBS tagged ops that retired but were discarded due to IBS fil…

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