Lines Matching full:were

117 …Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
127 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the…
137 …ounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the…
147 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM at…
157 …ounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on…
167         "BriefDescription": "Counts demand data reads that were supplied by DRAM.",
177 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,…
187 …"BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2,…
197 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, …
207 …"BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socke…
217 …"BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory contr…
227 … requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
237 …requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the…
247 … for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 ca…
257 …requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM at…
267 …requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on…
277 …ta cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.",
287 …a cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the…
297 …a cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the…
307 …a cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM at…
327 …"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local…
337 …"BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socke…
347 …Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the…
357 …Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the…
367 …"BriefDescription": "Counts hardware and software prefetches to all cache levels that were not sup…
377 …quests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
387 …uests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the…
397 …etches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 ca…
407 …and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the loc…
417 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM at…
427 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM at…
437 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM at…
447 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or…
457 …uests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on…
477 …"BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, …
510 …ycles while requests are outstanding - only cycles from when the requests were known to have misse…
529 …s while the requests are outstanding - only cycles from when the requests were known to have misse…