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/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Dmtk-wdt.txt3 The watchdog supports a pre-timeout interrupt that fires timeout-sec/2
8 - compatible should contain:
9 "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
10 "mediatek,mt2712-wdt": for MT2712
11 "mediatek,mt6582-wdt", "mediatek,mt6589-wdt": for MT6582
12 "mediatek,mt6589-wdt": for MT6589
13 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
14 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
15 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
16 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
[all …]
H A Dmediatek,mtk-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 The watchdog supports a pre-timeout interrupt that fires
14 timeout-sec/2 before the expiry.
17 - $ref: watchdog.yaml#
22 - enum:
23 - mediatek,mt2712-wdt
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H A Daspeed,ast2400-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@codeconstruct.com.au>
15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt
29 aspeed,reset-type:
32 - cpu
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H A Drealtek,otto-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sander Vanheule <sander@svanheule.net>
13 The timer has two timeout phases. Both phases have a maximum duration of 32
17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
20 During this phase, pinging the WDT has no effect, and a reset is
21 unavoidable, unless the WDT is disabled.
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H A Dmarvel.txt5 - Compatibility : "marvell,orion-wdt"
6 "marvell,armada-370-wdt"
7 "marvell,armada-xp-wdt"
8 "marvell,armada-375-wdt"
9 "marvell,armada-380-wdt"
11 - reg : Should contain two entries: first one with the
15 For "marvell,armada-375-wdt" and "marvell,armada-380-wdt":
17 - reg : A third entry is mandatory and should contain the
20 Clocks required for compatibles = "marvell,orion-wdt",
21 "marvell,armada-370-wdt":
[all …]
H A Dmeson-wdt.txt5 - compatible : depending on the SoC this should be one of:
6 "amlogic,meson6-wdt" on Meson6 SoCs
7 "amlogic,meson8-wdt" and "amlogic,meson6-wdt" on Meson8 SoCs
8 "amlogic,meson8b-wdt" on Meson8b SoCs
9 "amlogic,meson8m2-wdt" and "amlogic,meson8b-wdt" on Meson8m2 SoCs
10 - reg : Specifies base physical address and size of the registers.
13 - timeout-sec: contains the watchdog timeout in seconds.
17 wdt: watchdog@c1109900 {
18 compatible = "amlogic,meson6-wdt";
20 timeout-sec = <10>;
H A Dqcom-wdt.txt1 Qualcomm Krait Processor Sub-system (KPSS) Watchdog
2 ---------------------------------------------------
5 - compatible : shall contain only one of the following:
7 "qcom,kpss-wdt-msm8960"
8 "qcom,kpss-wdt-apq8064"
9 "qcom,kpss-wdt-ipq8064"
10 "qcom,kpss-wdt-ipq4019"
11 "qcom,kpss-timer"
12 "qcom,scss-timer"
13 "qcom,kpss-wdt"
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H A Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
16 the timeout interval, an interrupt is generated and the WDT state
19 expiration of the timeout interval, a WDT reset is generated.
[all …]
H A Ddavinci-wdt.txt1 Texas Instruments DaVinci/Keystone Watchdog Timer (WDT) Controller
4 - compatible : Should be "ti,davinci-wdt", "ti,keystone-wdt"
5 - reg : Should contain WDT registers location and length
8 - timeout-sec : Contains the watchdog timeout in seconds
9 - clocks : the clock feeding the watchdog timer.
11 See clock-bindings.txt
14 Davinci DM646x - https://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
15 Keystone - https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
19 wdt: wdt@2320000 {
20 compatible = "ti,davinci-wdt";
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H A Drenesas,wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/renesas,wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Watchdog Timer (WDT) Controller
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - items:
17 - enum:
18 - renesas,r7s72100-wdt # RZ/A1
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H A Dstarfive,jh7100-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
15 has only one timeout phase and reboots. And JH7110 watchdog has two
16 timeout phases. At the first phase, the signal of watchdog interrupt
18 the timeout value. And then, if counter decreases to 0 again and WDOGINT
25 - enum:
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H A Domap-wdt.txt1 TI Watchdog Timer (WDT) Controller for OMAP
4 - compatible : "ti,omap3-wdt" for OMAP3 or "ti,omap4-wdt" for OMAP4
5 - ti,hwmods : Name of the hwmod associated to the WDT
8 - timeout-sec : default watchdog timeout in seconds
12 wdt2: wdt@4a314000 {
13 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
H A Dsnps,dw-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jamie Iles <jamie@jamieiles.com>
13 - $ref: watchdog.yaml#
18 - const: snps,dw-wdt
19 - items:
20 - enum:
21 - rockchip,px30-wdt
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H A Daspeed-wdt.txt4 - compatible: must be one of:
5 - "aspeed,ast2400-wdt"
6 - "aspeed,ast2500-wdt"
7 - "aspeed,ast2600-wdt"
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H A Dnuvoton,npcm-wdt.txt3 Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
4 The watchdog supports a pre-timeout interrupt that fires 10ms before the
8 - compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
9 "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
10 "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
11 - reg : Offset and length of the register set for the device.
12 - interrupts : Contain the timer interrupt with flags for
16 - clocks : phandle of timer reference clock.
17 - clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
21 - timeout-sec : Contains the watchdog timeout in seconds
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H A Darm,sp805.txt3 SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
7 As SP805 WDT is a primecell IP, it follows the base bindings specified in
11 - compatible: Should be "arm,sp805" & "arm,primecell"
12 - reg: Should contain location and length for watchdog timer register
13 - clocks: Clocks driving the watchdog timer hardware. This list should be
15 wdog_clk can be equal to or be a sub-multiple of the apb_pclk
17 - clock-names: Shall be "wdog_clk" for first clock and "apb_pclk" for the
21 - interrupts: Should specify WDT interrupt number
22 - timeout-sec: Should specify default WDT timeout in seconds. If unset, the
23 default timeout is determined by the driver
[all …]
H A Dgpio-wdt.txt1 * GPIO-controlled Watchdog
4 - compatible: Should contain "linux,wdt-gpio".
5 - gpios: From common gpio binding; gpio connection to WDT reset pin.
6 - hw_algo: The algorithm used by the driver. Should be one of the
8 - toggle: Either a high-to-low or a low-to-high transition clears
9 the WDT counter. The watchdog timer is disabled when GPIO is
10 left floating or connected to a three-state buffer.
11 - level: Low or high level starts counting WDT timeout,
12 the opposite level disables the WDT. Active level is determined
14 - hw_margin_ms: Maximum time to reset watchdog circuit (milliseconds).
[all …]
H A Datmel-sama5d4-wdt.txt1 * Atmel SAMA5D4 Watchdog Timer (WDT) Controller
4 - compatible: "atmel,sama5d4-wdt" or "microchip,sam9x60-wdt"
5 - reg: base physical address and length of memory mapped region.
8 - timeout-sec: watchdog timeout value (in seconds).
9 - interrupts: interrupt number to the CPU.
10 - atmel,watchdog-type: should be "hardware" or "software".
15 - atmel,idle-halt: present if you want to stop the watchdog when the CPU is
22 - atmel,dbg-halt: present if you want to stop the watchdog when the CPU is
27 compatible = "atmel,sama5d4-wdt";
30 timeout-sec = <10>;
[all …]
H A Dlinux,wdt-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/linux,wdt-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-controlled Watchdog
10 - Guenter Roeck <linux@roeck-us.net>
11 - Robert Marko <robert.marko@sartura.hr>
15 const: linux,wdt-gpio
18 description: gpio connection to WDT reset pin
24 - description:
[all …]
H A Dgpio-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/gpio-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robert.marko@sartura.hr>
14 const: linux,wdt-gpio
18 description: GPIO connected to the WDT reset pin
24 - description:
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
27 to a three-state buffer.
[all …]
H A Dzte,zx2967-wdt.txt5 - compatible : should be one of the following.
6 * zte,zx296718-wdt
7 - reg : Specifies base physical address and size of the registers.
8 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - resets : Reference to the reset controller controlling the watchdog
14 - timeout-sec : Contains the watchdog timeout in seconds.
15 - zte,wdt-reset-sysctrl : Directs how to reset system by the watchdog.
19 * phandle of aon-sysctrl.
21 * configure value that be written to aon-sysctrl.
26 wdt: watchdog@1465000 {
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H A Dts4800-wdt.txt4 - compatible: must be "technologic,ts4800-wdt"
5 - syscon: phandle / integer array that points to the syscon node which
7 - phandle to FPGA's syscon
8 - offset to the watchdog register
11 - timeout-sec: contains the watchdog timeout in seconds.
16 compatible = "syscon", "simple-mfd";
18 reg-io-width = <2>;
20 wdt@e {
21 compatible = "technologic,ts4800-wdt";
23 timeout-sec = <10>;
H A Dcdns,wdt-r1p2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
15 a programmable reset period. The timeout period varies from 1 ms
19 - $ref: watchdog.yaml#
24 - cdns,wdt-r1p2
35 reset-on-timeout:
42 - compatible
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H A Datmel-wdt.txt3 ** at91sam9-wdt
6 - compatible: must be "atmel,at91sam9260-wdt".
7 - reg: physical base address of the controller and length of memory mapped
9 - clocks: phandle to input clock.
12 - timeout-sec: contains the watchdog timeout in seconds.
13 - interrupts : Should contain WDT interrupt.
14 - atmel,max-heartbeat-sec : Should contain the maximum heartbeat value in
17 - atmel,min-heartbeat-sec : Should contain the minimum heartbeat value in
18 seconds. This value must be smaller than the max-heartbeat-sec value.
20 - atmel,watchdog-type : Should be "hardware" or "software". Hardware watchdog
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx_wdog.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
73 {"fsl,imx6sx-wdt", 1},
74 {"fsl,imx6sl-wdt", 1},
75 {"fsl,imx6q-wdt", 1},
76 {"fsl,imx53-wdt", 1},
77 {"fsl,imx51-wdt", 1},
78 {"fsl,imx50-wdt", 1},
79 {"fsl,imx35-wdt", 1},
80 {"fsl,imx27-wdt", 1},
[all …]

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