1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MediaTek IOMMU Architecture Implementation 8 9maintainers: 10 - Yong Wu <yong.wu@mediatek.com> 11 12description: |+ 13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and 14 this M4U have two generations of HW architecture. Generation one uses flat 15 pagetable, and only supports 4K size page mapping. Generation two uses the 16 ARM Short-Descriptor translation table format for address translation. 17 18 About the M4U Hardware Block Diagram, please check below: 19 20 EMI (External Memory Interface) 21 | 22 m4u (Multimedia Memory Management Unit) 23 | 24 +--------+ 25 | | 26 gals0-rx gals1-rx (Global Async Local Sync rx) 27 | | 28 | | 29 gals0-tx gals1-tx (Global Async Local Sync tx) 30 | | Some SoCs may have GALS. 31 +--------+ 32 | 33 SMI Common(Smart Multimedia Interface Common) 34 | 35 +----------------+------- 36 | | 37 | gals-rx There may be GALS in some larbs. 38 | | 39 | | 40 | gals-tx 41 | | 42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). 43 (display) (vdec) 44 | | 45 | | 46 +-----+-----+ +----+----+ 47 | | | | | | 48 | | |... | | | ... There are different ports in each larb. 49 | | | | | | 50 OVL0 RDMA0 WDMA0 MC PP VLD 51 52 As above, The Multimedia HW will go through SMI and M4U while it 53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain 54 smi local arbiter and smi common. It will control whether the Multimedia 55 HW should go through the m4u for translation or bypass it and talk 56 directly with EMI. And also SMI help control the power domain and clocks for 57 each local arbiter. 58 59 Normally we specify a local arbiter(larb) for each multimedia HW 60 like display, video decode, and camera. And there are different ports 61 in each larb. Take a example, There are many ports like MC, PP, VLD in the 62 video decode local arbiter, all these ports are according to the video HW. 63 64 In some SoCs, there may be a GALS(Global Async Local Sync) module between 65 smi-common and m4u, and additional GALS module between smi-larb and 66 smi-common. GALS can been seen as a "asynchronous fifo" which could help 67 synchronize for the modules in different clock frequency. 68 69properties: 70 compatible: 71 oneOf: 72 - enum: 73 - mediatek,mt2701-m4u # generation one 74 - mediatek,mt2712-m4u # generation two 75 - mediatek,mt6779-m4u # generation two 76 - mediatek,mt6795-m4u # generation two 77 - mediatek,mt6893-iommu-mm # generation two 78 - mediatek,mt8167-m4u # generation two 79 - mediatek,mt8173-m4u # generation two 80 - mediatek,mt8183-m4u # generation two 81 - mediatek,mt8186-iommu-mm # generation two 82 - mediatek,mt8188-iommu-vdo # generation two 83 - mediatek,mt8188-iommu-vpp # generation two 84 - mediatek,mt8188-iommu-infra # generation two 85 - mediatek,mt8189-iommu-apu # generation two 86 - mediatek,mt8189-iommu-infra # generation two 87 - mediatek,mt8189-iommu-mm # generation two 88 - mediatek,mt8192-m4u # generation two 89 - mediatek,mt8195-iommu-vdo # generation two 90 - mediatek,mt8195-iommu-vpp # generation two 91 - mediatek,mt8195-iommu-infra # generation two 92 - mediatek,mt8365-m4u # generation two 93 94 - description: mt7623 generation one 95 items: 96 - const: mediatek,mt7623-m4u 97 - const: mediatek,mt2701-m4u 98 99 reg: 100 maxItems: 1 101 102 interrupts: 103 maxItems: 1 104 105 clocks: 106 items: 107 - description: bclk is the block clock. 108 109 clock-names: 110 items: 111 - const: bclk 112 113 mediatek,infracfg: 114 $ref: /schemas/types.yaml#/definitions/phandle 115 description: The phandle to the mediatek infracfg syscon 116 117 mediatek,larbs: 118 $ref: /schemas/types.yaml#/definitions/phandle-array 119 minItems: 1 120 maxItems: 32 121 items: 122 maxItems: 1 123 description: | 124 List of phandle to the local arbiters in the current Socs. 125 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort 126 according to the local arbiter index, like larb0, larb1, larb2... 127 128 '#iommu-cells': 129 const: 1 130 description: | 131 This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as 132 defined in 133 dt-binding/memory/mediatek,mt8188-memory-port.h for mt8188, 134 dt-binding/memory/mediatek,mt8189-memory-port.h for mt8189, 135 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, 136 dt-binding/memory/mt2712-larb-port.h for mt2712, 137 dt-binding/memory/mt6779-larb-port.h for mt6779, 138 dt-binding/memory/mt6795-larb-port.h for mt6795, 139 dt-binding/memory/mediatek,mt6893-memory-port.h for mt6893, 140 dt-binding/memory/mt8167-larb-port.h for mt8167, 141 dt-binding/memory/mt8173-larb-port.h for mt8173, 142 dt-binding/memory/mt8183-larb-port.h for mt8183, 143 dt-binding/memory/mt8186-memory-port.h for mt8186, 144 dt-binding/memory/mt8192-larb-port.h for mt8192. 145 dt-binding/memory/mt8195-memory-port.h for mt8195. 146 dt-binding/memory/mediatek,mt8365-larb-port.h for mt8365. 147 148 power-domains: 149 maxItems: 1 150 151required: 152 - compatible 153 - reg 154 - interrupts 155 - '#iommu-cells' 156 157allOf: 158 - if: 159 properties: 160 compatible: 161 contains: 162 enum: 163 - mediatek,mt2701-m4u 164 - mediatek,mt2712-m4u 165 - mediatek,mt6795-m4u 166 - mediatek,mt6893-iommu-mm 167 - mediatek,mt8173-m4u 168 - mediatek,mt8186-iommu-mm 169 - mediatek,mt8188-iommu-vdo 170 - mediatek,mt8188-iommu-vpp 171 - mediatek,mt8189-iommu-mm 172 - mediatek,mt8192-m4u 173 - mediatek,mt8195-iommu-vdo 174 - mediatek,mt8195-iommu-vpp 175 176 then: 177 required: 178 - clocks 179 180 - if: 181 properties: 182 compatible: 183 enum: 184 - mediatek,mt6893-iommu-mm 185 - mediatek,mt8186-iommu-mm 186 - mediatek,mt8188-iommu-vdo 187 - mediatek,mt8188-iommu-vpp 188 - mediatek,mt8189-iommu-mm 189 - mediatek,mt8192-m4u 190 - mediatek,mt8195-iommu-vdo 191 - mediatek,mt8195-iommu-vpp 192 193 then: 194 required: 195 - power-domains 196 197 - if: 198 properties: 199 compatible: 200 contains: 201 enum: 202 - mediatek,mt2712-m4u 203 - mediatek,mt6795-m4u 204 - mediatek,mt8173-m4u 205 206 then: 207 required: 208 - mediatek,infracfg 209 210 - if: # The IOMMUs don't have larbs. 211 not: 212 properties: 213 compatible: 214 contains: 215 enum: 216 - mediatek,mt8188-iommu-infra 217 - mediatek,mt8189-iommu-apu 218 - mediatek,mt8189-iommu-infra 219 - mediatek,mt8195-iommu-infra 220 221 then: 222 required: 223 - mediatek,larbs 224 225additionalProperties: false 226 227examples: 228 - | 229 #include <dt-bindings/clock/mt8173-clk.h> 230 #include <dt-bindings/interrupt-controller/arm-gic.h> 231 232 iommu: iommu@10205000 { 233 compatible = "mediatek,mt8173-m4u"; 234 reg = <0x10205000 0x1000>; 235 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 236 clocks = <&infracfg CLK_INFRA_M4U>; 237 clock-names = "bclk"; 238 mediatek,infracfg = <&infracfg>; 239 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 240 <&larb3>, <&larb4>, <&larb5>; 241 #iommu-cells = <1>; 242 }; 243