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/linux/Documentation/devicetree/bindings/w1/
H A Dw1-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART 1-Wire Bus
10 - Christoph Winklhofer <cj.winklhofer@gmail.com>
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
16 The UART peripheral must support full-duplex and operate in open-drain
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
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/linux/drivers/w1/masters/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # 1-wire bus master configuration
6 menu "1-wire Bus Masters"
9 tristate "AMD AXI 1-wire bus host"
11 Say Y here is you want to support the AMD AXI 1-wire IP core.
20 tristate "Matrox G400 transport layer for 1-wire"
23 Say Y here if you want to communicate with your 1-wire devices
30 tristate "DS2490 USB <-> W1 transport layer for 1-wire"
33 Say Y here if you want to have a driver for DS2490 based USB <-> W1 bridges,
40 tristate "Maxim DS2482 I2C to 1-Wire bridge"
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for 1-wire bus master drivers.
6 obj-$(CONFIG_W1_MASTER_AMD_AXI) += amd_axi_w1.o
7 obj-$(CONFIG_W1_MASTER_MATROX) += matrox_w1.o
8 obj-$(CONFIG_W1_MASTER_DS2490) += ds2490.o
9 obj-$(CONFIG_W1_MASTER_DS2482) += ds2482.o
10 obj-$(CONFIG_W1_MASTER_MXC) += mxc_w1.o
12 obj-$(CONFIG_W1_MASTER_GPIO) += w1-gpio.o
13 obj-$(CONFIG_HDQ_MASTER_OMAP) += omap_hdq.o
14 obj-$(CONFIG_W1_MASTER_SGI) += sgi_w1.o
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/linux/Documentation/w1/masters/
H A Dw1-uart.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 .. _"Using a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/u…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
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/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-axg-jethome-jethub-j1xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "meson-axg.dtsi"
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/thermal/thermal.h>
19 serial2 = &uart_AO_B; /* External UART (Wireless Module) */
24 stdout-path = "serial0:115200n8";
27 reserved-memory {
33 emmc_pwrseq: emmc-pwrseq {
34 compatible = "mmc-pwrseq-emmc";
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/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-arcom-vulcan.dts1 // SPDX-License-Identifier: ISC
8 /dts-v1/;
10 #include "intel-ixp42x.dtsi"
11 #include <dt-bindings/input/input.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
27 stdout-path = "uart0:115200n8";
35 compatible = "w1-gpio";
42 compatible = "intel,ixp4xx-flash", "cfi-flash";
43 bank-width = <2>;
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/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-btt3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
7 #include "imx28-lwe.dtsi"
12 compatible = "lwn,imx28-btt3", "fsl,imx28";
24 compatible = "powertip,hx8238a", "panel-dpi";
25 power-supply = <&reg_3v3>;
26 width-mm = <70>;
27 height-mm = <52>;
29 panel-timing {
30 clock-frequency = <6500000>;
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H A Dimx28-tx28.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 model = "Ka-Ro electronics TX28 module";
34 reg = <0x40000000 0>; /* will be filled in by U-Boot */
38 compatible = "w1-gpio";
43 reg_usb0_vbus: regulator-usb0-vbus {
44 compatible = "regulator-fixed";
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/linux/drivers/pinctrl/aspeed/
H A Dpinmux-aspeed.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * read-only).
23 * SoC Multi-function Pin Expression Examples
24 * ------------------------------------------
34 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
36 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
38 * C5 is a multi-signal pin (high and low priority signals). Here we touch
41 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
43 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
45 * E19 is a single-signal pin with two functions that influence the active
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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