Home
last modified time | relevance | path

Searched +full:voltage +full:- +full:frequency (Results 1 – 25 of 784) sorted by relevance

12345678910>>...32

/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,admv1013.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 24 GHz to 44 GHz frequency range.
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
[all …]
H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 24 GHz to 44 GHz frequency range.
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
[all …]
/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/devfreq-event.h>
101 * struct dmc_opp_table - Operating level desciption
102 * @freq_hz: target frequency in Hz
103 * @volt_uv: target voltage in uV
105 * Covers frequency and voltage settings of the DMC operating mode.
113 * struct exynos5_dmc - main structure describing DMC device
120 * @lock: protects curr_rate and frequency/voltage setting section
121 * @curr_rate: current frequency
122 * @curr_volt: current voltage
[all …]
/linux/Documentation/power/
H A Dopp.rst5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
24 need to function at their highest performing frequency all the time. To
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
26 domains to run at lower voltage and frequency while other domains run at
27 voltage/frequency pairs that are higher.
29 The set of discrete tuples consisting of frequency and voltage pairs that
36 {300MHz at minimum voltage of 1V}, {800MHz at minimum voltage of 1.2V},
37 {1GHz at minimum voltage of 1.3V}
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v1.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v1.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
19 This binding only supports voltage-frequency pairs.
24 clock-latency:
30 voltage-tolerance:
34 The voltage tolerance in percent. Use OPP tables for new designs instead.
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dovti,ov02a10.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Dongchun Zhu <dongchun.zhu@mediatek.com>
13 description: |-
14 The Omnivision OV02A10 is a low-cost, high performance, 1/5-inch, 2 megapixel
17 @ 1600x1200 (UXGA) resolution transferred over a 1-lane MIPI interface. The
18 sensor output is available via CSI-2 serial data output.
21 - $ref: /schemas/media/video-interface-devices.yaml#
33 clock-names:
[all …]
H A Daptina,mt9p031.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
15 simple two-wire serial interface.
20 - aptina,mt9p006
21 - aptina,mt9p031
22 - aptina,mt9p031m
[all …]
H A Dmipi-ccs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2014--2020 Intel Corporation
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sakari Ailus <sakari.ailus@linux.intel.com>
17 <URL:https://www.mipi.org/specifications/camera-command-set>.
24 Documentation/devicetree/bindings/media/video-interfaces.txt .
29 - items:
30 - const: mipi-ccs-1.1
[all …]
H A Dsamsung,s5k6a3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13 S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data
26 clock-names:
28 - const: extclk
30 clock-frequency:
32 description: extclk clock frequency
38 afvdd-supply:
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dadi,ltc2672.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
11 - Kim Seer Paller <kimseer.paller@analog.com>
14 Analog Devices LTC2672 5 channel, 12-/16-Bit, 300mA DAC
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ltc2672.pdf
20 - adi,ltc2672
25 spi-max-frequency:
28 vcc-supply:
[all …]
H A Drohm,bd79703.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Matti Vaittinen <mazziesaccount@gmail.com>
14 The ROHM BD7970[0,1,2,3] are 8-bit DACs. The BD79700 has 2 channels,
17 …fscdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79702fv-lb_bd79703fv-lb-e.pdf
19 …cdn.rohm.com/en/products/databook/datasheet/ic/data_converter/dac/bd79700fvm-lb_bd79701fvm-lb-e.pdf
24 - rohm,bd79700
25 - rohm,bd79701
26 - rohm,bd79702
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,wcd934x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Qualcomm WCD9340/WCD9341 Codec is a standalone Hi-Fi audio codec IC.
14 It has in-built Soundwire controller, pin controller, interrupt mux and
27 reset-gpios:
31 slim-ifc-dev:
38 clock-names:
41 vdd-buck-supply:
[all …]
H A Dcs42l56.txt5 - compatible : "cirrus,cs42l56"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VCP-supply, VLDO-supply : power supplies for the device,
14 - cirrus,gpio-nreset : GPIO controller's phandle and the number
17 - cirrus,chgfreq-divisor : Values used to set the Charge Pump Frequency.
19 register, not the actual frequency. The frequency is determined by the following.
20 Frequency = MCLK / 4 * (N+2)
22 MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.
24 - cirrus,ain1a-ref-cfg, ain1b-ref-cfg : boolean, If present, AIN1A or AIN1B are configured
25 as a pseudo-differential input referenced to AIN1REF/AIN3A.
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgm20b.c89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
136 /* safe frequency we can use at minimum voltage */
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
168 pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) & in gm20b_pllg_read_mnp()
175 struct nvkm_device *device = clk->base.base.subdev.device; in gm20b_pllg_write_mnp()
178 pll->sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT); in gm20b_pllg_write_mnp()
[all …]
/linux/arch/arm/mach-omap2/
H A Domap_opp_data.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2010 Texas Instruments Incorporated - https://www.ti.com/
16 #include "voltage.h"
25 * struct omap_opp_def - OMAP OPP Definition
27 * @freq: Frequency in hertz corresponding to this OPP
28 * @u_volt: Nominal voltage in microvolts corresponding to this OPP
29 * @default_available: True/false - is this OPP available by default
31 * OMAP SOCs have a standard set of tuples consisting of frequency and voltage
32 * pairs that the device will support per voltage domain. This is called
35 * domain, you can have a set of {frequency, voltage} pairs and this is denoted
[all …]
/linux/tools/perf/pmu-events/arch/x86/jaketown/
H A Duncore-power.json88 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
97 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
106 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
115 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
124 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
133 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
142 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
151 …"PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
155 "BriefDescription": "Frequency Residency",
160 …frequency greater than or equal to the frequency that is configured in the filter. One can use al…
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-cfa10049.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
8 * need to include the CFA-10036 DTS.
10 #include "imx28-cfa10036.dts"
13 model = "Crystalfontz CFA-10049 Board";
17 compatible = "i2c-mux-gpio";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&i2cmux_pins_cfa10049>;
[all …]
H A Dimx28-tx28.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * Copyright 2013-2017 Lothar Waßmann <LW@KARO-electronics.de>
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 model = "Ka-Ro electronics TX28 module";
34 reg = <0x40000000 0>; /* will be filled in by U-Boot */
38 compatible = "w1-gpio";
43 reg_usb0_vbus: regulator-usb0-vbus {
44 compatible = "regulator-fixed";
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-spi-slot.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-spi-slot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml
14 - $ref: /schemas/spi/spi-peripheral-props.yaml
21 const: mmc-spi-slot
29 voltage-ranges:
30 $ref: /schemas/types.yaml#/definitions/uint32-matrix
[all …]
H A Dfsl,esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Frank Li <Frank.Li@nxp.com>
19 - enum:
20 - fsl,mpc8536-esdhc
21 - fsl,mpc8378-esdhc
22 - fsl,p2020-esdhc
23 - fsl,p4080-esdhc
24 - fsl,t1040-esdhc
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dmps,mp886x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Monolithic Power Systems MP8867/MP8869 voltage regulator
10 - Jisheng Zhang <jszhang@kernel.org>
13 - $ref: regulator.yaml#
18 - mps,mp8867
19 - mps,mp8869
24 enable-gpios:
28 mps,fb-voltage-divider:
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
[all …]
/linux/drivers/thermal/
H A Ddevfreq_cooling.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2014-2015 ARM Limited
9 * - If OPPs are added or removed after devfreq cooling has
28 * struct devfreq_cooling_device - Devfreq cooling device
46 * @req_max_freq: PM QoS request for limiting the maximum frequency
67 struct devfreq_cooling_device *dfc = cdev->devdata; in devfreq_cooling_get_max_state()
69 *state = dfc->max_state; in devfreq_cooling_get_max_state()
77 struct devfreq_cooling_device *dfc = cdev->devdata; in devfreq_cooling_get_cur_state()
79 *state = dfc->cooling_state; in devfreq_cooling_get_cur_state()
87 struct devfreq_cooling_device *dfc = cdev->devdata; in devfreq_cooling_set_cur_state()
[all …]
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu14_driver_if_v14_0_0.h42 uint16_t Vid; // min voltage in SVI3 VID
113 uint32_t Voltage; member
119 //Voltage in milli volts with 2 fractional bits
148 //Voltage in milli volts with 2 fractional bits
178 uint16_t CoreFrequency[16]; //Target core frequency [MHz]
180 uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C]
181 uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C]
182 uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C]
185 uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz]
186 uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz]
[all …]
/linux/drivers/cpufreq/
H A Dpowernow-k8.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * (c) 2003-2006 Advanced Micro Devices, Inc.
9 u32 numps; /* number of p-states */
10 u32 batps; /* number of p-states supported on battery */
13 * vid/fid pairings, but are modified during the ->target() call
15 u32 rvo; /* ramp voltage offset */
18 u32 vstable; /* voltage stabilization time, units 20 us */
26 /* the powernow_table includes all frequency and vid/fid pairings:
28 * frequency is in kHz */
32 * used to determine valid frequency/vid/fid states */
[all …]

12345678910>>...32