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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dmediatek-vcodec.txt1 Mediatek Video Codec
3 Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
7 - compatible : must be one of the following string:
8 "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
9 "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
10 "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
11 "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
12 "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
13 "mediatek,mt8183-vcodec-dec" for MT8183 decoder.
14 "mediatek,mt8195-vcodec-enc" for MT8195 encoder.
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H A Dallegro,al5e.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allegro DVT Video IP Codecs
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may
16 Each actual codec engine is controlled by a microcontroller (MCU). Host
23 - items:
24 - const: allegro,al5e-1.1
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H A Dallegro.txt1 Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
5 Each actual codec engines is controlled by a microcontroller (MCU). Host
10 - compatible: value should be one of the following
11 "allegro,al5e-1.1", "allegro,al5e": encoder IP core
12 "allegro,al5d-1.1", "allegro,al5d": decoder IP core
13 - reg: base and length of the memory mapped register region and base and
15 - reg-names: must include "regs" and "sram"
16 - interrupts: shared interrupt from the MCUs to the processing system
17 - clocks: must contain an entry for each entry in clock-names
18 - clock-names: must include "core_clk", "mcu_clk", "m_axi_core_aclk",
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H A Dmediatek,vcodec-subdev-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subde
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H A Dnxp,imx8mq-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs.
19 - const: nxp,imx8mq-vpu
21 - const: nxp,imx8mq-vpu-g1
22 - const: nxp,imx8mq-vpu-g2
23 - const: nxp,imx8mm-vpu-g1
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H A Dcoda.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Chips&Media Coda multi-standard codec IP
10 - Philipp Zabel <p.zabel@pengutronix.de>
12 description: |-
13 Coda codec IPs are present in i.MX SoCs in various versions,
14 called VPU (Video Processing Unit).
19 - items:
20 - const: fsl,imx27-vpu
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H A Dallwinner,sun4i-a10-video-engine.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Video Engine
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun4i-a10-video-engine
17 - allwinner,sun5i-a13-video-engine
18 - allwinner,sun7i-a20-video-engine
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H A Dallwinner,sun50i-h6-vpu-g2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Hantro G2 VPU codec implemented on Allwinner H6 SoC
11 - Jernej Skrabec <jernej.skrabec@gmail.com>
14 Hantro G2 video decode accelerator present on Allwinner H6 SoC.
18 const: allwinner,sun50i-h6-vpu-g2
28 - description: Bus Clock
29 - description: Module Clock
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H A Dqcom,msm8916-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,msm8916-venus.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Dqcom,sc7180-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sc7180-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7180 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sc7180-venus
23 power-domains:
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H A Dqcom,sc7280-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sc7280-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SC7280 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus Iris2 IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sc7280-venus
23 power-domains:
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H A Drockchip,vdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Video Decoder (VDec)
10 - Heiko Stuebner <heiko@sntech.de>
12 description: |-
13 The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264,
19 - const: rockchip,rk3399-vdec
20 - items:
21 - enum:
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H A Dqcom,sdm845-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sdm845-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM845 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sdm845-venus
23 power-domains:
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H A Dqcom,sdm845-venus-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sdm845-venus-v
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H A Dqcom,sm8250-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sm8250-venus.yaml#
5 $schema: http://devicetree.org/meta-schema
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H A Dqcom,msm8996-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,msm8996-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8996 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
13 The Venus IP is a video encode and decode accelerator present
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,msm8996-venus
23 power-domains:
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H A Dqcom,sdm660-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sdm660-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDM660 Venus video encode and decode accelerators
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
11 - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
14 The Venus IP is a video encode and decode accelerator present
18 - $ref: qcom,venus-common.yaml#
22 const: qcom,sdm660-venus
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H A Dmediatek-vpu.txt1 * Mediatek Video Processor Unit
3 Video Processor Unit is a HW video controller. It controls HW Codec including
7 - compatible: "mediatek,mt8173-vpu"
8 - reg: Must contain an entry for each entry in reg-names.
9 - reg-names: Must include the following entries:
12 - interrupts: interrupt number to the cpu.
13 - clocks : clock name from clock manager
14 - clock-names: must be main. It is the main clock of VPU
17 - memory-region: phandle to a node describing memory (see
18 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
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H A Dnvidia,tegra-vde.txt1 NVIDIA Tegra Video Decoder Engine
4 - compatible : Must contain one of the following values:
5 - "nvidia,tegra20-vde"
6 - "nvidia,tegra30-vde"
7 - "nvidia,tegra114-vde"
8 - "nvidia,tegra124-vde"
9 - "nvidia,tegra132-vde"
10 - reg : Must contain an entry for each entry in reg-names.
11 - reg-names : Must include the following entries:
12 - sxe
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H A Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Video Decoder Engine
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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H A Dcoda.txt1 Chips&Media Coda multi-standard codec IP
4 Coda codec IPs are present in i.MX SoCs in various versions,
5 called VPU (Video Processing Unit).
8 - compatible : should be "fsl,<chip>-src" for i.MX SoCs:
9 (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
10 (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
11 (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
12 (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
13 - reg: should be register base and length as documented in the
15 - interrupts : Should contain the VPU interrupt. For CODA960,
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H A Drockchip,rk3568-vepu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/rockchip,rk3568-vepu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
14 Hantro G1 video encode-only accelerators present on Rockchip SoCs.
19 - rockchip,rk3568-vepu
30 clock-names:
32 - const: aclk
33 - const: hclk
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/freebsd/contrib/file/magic/Magdir/
H A Driff2 #------------------------------------------------------------------------------
8 # http://www-mmsp.ece.mcgill.ca/Documents/AudioFormats/WAVE/Docs/riffmci.pdf
9 # https://www.iana.org/assignments/wave-avi-codec-registry/wave-avi-codec-registry.xml
13 0 name riff-wave
21 >0 leshort 0x06 \b, ITU G.711 A-law
22 >0 leshort 0x07 \b, ITU G.711 mu-law
115 >0 leshort 0x1100 \b, LH Codec
129 0 name riff-walk
132 >>>8 use riff-wave
134 >>&(4.l+4) use riff-walk
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxl-s905x-p212.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "meson-gxl-s905x-p212.dtsi"
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "amlogic,p212", "amlogic,s905x", "amlogic,meson-gxl";
16 dio2133: analog-amplifier {
17 compatible = "simple-audio-amplifier";
18 sound-name-prefix = "AU2";
19 VCC-supply = <&hdmi_5v>;
20 enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dsii902x.txt4 - compatible: "sil,sii9022"
5 - reg: i2c address of the bridge
8 - interrupts: describe the interrupt line used to inform the host
10 - reset-gpios: OF device-tree gpio specification for RST_N pin.
11 - iovcc-supply: I/O Supply Voltage (1.8V or 3.3V)
12 - cvcc12-supply: Digital Core Supply Voltage (1.2V)
15 - #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
18 - sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3
23 pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
28 - clocks: phandle and clock specifier for each clock listed in
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