Searched +full:versal2 +full:- +full:mdb +full:- +full:host (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>13 - $ref: /schemas/pci/pci-host-bridge.yaml#14 - $ref: /schemas/pci/snps,dw-pcie.yaml#18 const: amd,versal2-mdb-host22 - description: MDB System Level Control and Status Register (SLCR) Base[all …]
1 # SPDX-License-Identifier: GPL-2.03 menu "DesignWare-based PCIe controllers"39 required only for DT-based platforms. ACPI platforms with the43 bool "AMD MDB Versal2 PCIe controller"49 Versal2 SoCs. The AMD MDB Versal2 PCIe controller is based on50 DesignWare IP and therefore the driver re-uses the DesignWare61 and therefore the driver re-uses the DesignWare core functions to68 bool "Axis ARTPEC-6 PCIe controller (host mode)"74 Enables support for the PCIe controller in the ARTPEC-6 SoC to work in75 host mode. This uses the DesignWare core.[all …]
1 // SPDX-License-Identifier: GPL-2.03 * PCIe host controller driver for AMD MDB PCIe Bridge5 * Copyright (C) 2024-2025, Advanced Micro Devices, Inc.22 #include "pcie-designware.h"55 * struct amd_mdb_pcie - PCIe port information57 * @slcr: MDB System Level Control and Status Register (SLCR) base59 * @mdb_domain: MDB IRQ domain pointer78 struct dw_pcie *pci = &pcie->pci; in amd_mdb_intx_irq_mask()79 struct dw_pcie_rp *port = &pci->pp; in amd_mdb_intx_irq_mask()83 raw_spin_lock_irqsave(&port->lock, flags); in amd_mdb_intx_irq_mask()[all …]