Searched +full:versal +full:- +full:clk (Results 1 – 14 of 14) sorted by relevance
/linux/Documentation/devicetree/bindings/clock/ |
H A D | xlnx,versal-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx Versal clock controller 10 - Michal Simek <michal.simek@amd.com> 13 The clock controller is a hardware block of Xilinx versal clock tree. It 20 - enum: 21 - xlnx,versal-clk 22 - xlnx,zynqmp-clk [all …]
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H A D | xlnx,clocking-wizard.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> 13 The clocking wizard is a soft ip clocking block of Xilinx versal. It 20 - xlnx,clocking-wizard 21 - xlnx,clocking-wizard-v5.2 22 - xlnx,clocking-wizard-v6.0 23 - xlnx,versal-clk-wizard [all …]
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/linux/Documentation/devicetree/bindings/firmware/xilinx/ |
H A D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nava kishore Manne <nava.kishore.manne@amd.com> 12 description: The zynqmp-firmware node describes the interface to platform 23 - description: For implementations complying for Zynq Ultrascale+ MPSoC. 24 const: xlnx,zynqmp-firmware 26 - description: For implementations complying for Versal. 27 const: xlnx,versal-firmware [all …]
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/linux/Documentation/devicetree/bindings/mmc/ |
H A D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Adrian Hunter <adrian.hunter@intel.com> 13 - $ref: mmc-controller.yaml# 14 - if: 18 const: arasan,sdhci-5.1 21 - phys 22 - phy-names 23 - if: [all …]
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/linux/drivers/watchdog/ |
H A D | xilinx_wwdt.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Window watchdog device driver for Xilinx Versal WWDT 5 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. 8 #include <linux/clk.h> 57 * struct xwwdt_device - Watchdog device structure 79 struct watchdog_device *xilinx_wwdt_wdd = &xdev->xilinx_wwdt_wdd; in xilinx_wwdt_start() 82 spin_lock(&xdev->spinlock); in xilinx_wwdt_start() 84 iowrite32(XWWDT_MWR_MASK, xdev->base + XWWDT_MWR_OFFSET); in xilinx_wwdt_start() 85 iowrite32(~(u32)XWWDT_ESR_WEN_MASK, xdev->base + XWWDT_ESR_OFFSET); in xilinx_wwdt_start() 86 iowrite32((u32)xdev->closed_timeout, xdev->base + XWWDT_FWR_OFFSET); in xilinx_wwdt_start() [all …]
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/linux/Documentation/devicetree/bindings/net/ |
H A D | cdns,macb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 - Claudiu Beznea <claudiu.beznea@microchip.com> 16 - items: 17 - enum: 18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC 19 - const: cdns,emac # Generic 21 - items: [all …]
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/linux/Documentation/devicetree/bindings/usb/ |
H A D | dwc3-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Mubin Sayyed <mubin.sayyed@amd.com> 11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> 16 - enum: 17 - xlnx,zynqmp-dwc3 18 - xlnx,versal-dwc3 22 "#address-cells": [all …]
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/linux/drivers/clk/zynqmp/ |
H A D | clkc.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2019 Xilinx 7 * Based on drivers/clk/zynq/clkc.c 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 19 #include "clk-zynqmp.h" 49 * struct clock_parent - Clock parent 61 * struct zynqmp_clock - Clock 141 * zynqmp_is_valid_clock() - Check whether clock is valid or not 149 return -ENODEV; in zynqmp_is_valid_clock() [all …]
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/linux/drivers/usb/dwc3/ |
H A D | dwc3-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver 12 #include <linux/clk.h> 15 #include <linux/dma-mapping.h> 22 #include <linux/firmware/xlnx-zynqmp.h> 59 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst() 66 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); in dwc3_xlnx_mask_phy_rst() 71 struct device *dev = priv_data->dev; in dwc3_xlnx_init_versal() 81 /* Assert and De-assert reset */ in dwc3_xlnx_init_versal() 90 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); in dwc3_xlnx_init_versal() [all …]
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/linux/drivers/gpio/ |
H A D | gpio-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 9 #include <linux/clk.h> 20 #define DRIVER_NAME "zynq-gpio" 46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1) 49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1) 52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1) 55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1) 58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1) 61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1) [all …]
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/linux/drivers/remoteproc/ |
H A D | xlnx_r5_remoteproc.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <dt-bindings/power/xlnx-zynqmp-power.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/firmware/xlnx-zynqmp.h> 12 #include <linux/mailbox/zynqmp-ipi-message.h> 34 * reflects possible values of xlnx,cluster-mode dt-property 38 LOCKSTEP_MODE = 1, /* cores execute same code in lockstep,clk-for-clk */ 43 * struct mem_bank_data - Memory Bank description 48 * @pm_domain_id: Power-domains id of memory bank for firmware to turn on/off 60 * struct zynqmp_sram_bank - sram bank description [all …]
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/linux/drivers/spi/ |
H A D | spi-cadence-quadspi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved. 6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved. 7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 9 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 16 #include <linux/firmware/xlnx-zynqmp.h> 30 #include <linux/spi/spi-mem.h> 33 #define CQSPI_NAME "cadence-qspi" 78 struct clk *clk; member [all …]
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/linux/drivers/net/ethernet/cadence/ |
H A D | macb_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2004-2006 Atmel Corporation 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 25 #include <linux/dma-mapping.h> 40 #include <linux/firmware/xlnx-zynqmp.h> 58 * (bp)->rx_ring_size) 64 * (bp)->tx_ring_size) 67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) 78 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -… [all …]
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/linux/ |
H A D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org 88 F: drivers/scsi/3w-* [all …]
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